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| CD4017BC Datasheet, PDF (4/10 Pages) Fairchild Semiconductor – Decade Counter/Divider with 10 Decoded Outputs . Divide-by-8 Counter/Divider with 8 Decoded Outputs | |||
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DC Electrical Characteristics CD4017BC CD4022BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b40 C
a25
a85 C
Units
Min Max Min Typ Max Min Max
VIL
Low Level
lIOl k 1 0 mA
Input Voltage
VDD e 5V VO e 0 5V or 4 5V
15
VDD e 10V VO e 1 0V or 9 0V
30
VDD e 15V VO e 1 5V or 13 5V
40
VIH
High Level
lIOl k 1 0 mA
Input Voltage
VDD e 5V VO e 0 5V or 4 5V
35
35
VDD e 10V VO e 1 0V or 9 0V 7 0
70
VDD e 15V VO e 1 5V or 13 5V 11 0
11 0
15
15 V
30
30 V
40
40 V
35
V
70
V
11 0
V
IOL
Low Level Output VDD e 5V VO e 0 4V
Current (Note 3) VDD e 10V VO e 0 5V
VDD e 15V VO e 1 5V
0 52
13
36
0 44 0 88
11
2 25
30
88
0 36
mA
09
mA
24
mA
IOH
High Level Output VDD e 5V VO e 4 6V
b0 2
b0 16 b0 36
b0 12
mA
Current (Note 3)
VDD e 10V VO e 9 5V
VDD e 15V VO e 13 5V
IIN
Input Current
VDD e 15V VIN e 0V
VDD e 15V VIN e 15V
b0 5
b0 4 b0 9
b0 3
mA
b1 4
b1 2 b3 5
b1 0
mA
b0 3
03
b10b5 b0 3
10b5 0 3
b1 0 mA
1 0 mA
Note 1 ââAbsolute Maximum Ratingsââ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The table of ââRecommended Operating Conditionsââ and ââElectrical Characteristicsââ provides condtions for actual device
operation
Note 2 VSS e 0V unless otherwise specified
Note 3 IOL and IOH are tested one output at a time
AC Electrical Characteristics te TA e 25 C CL e 50 pF RL e 200k trCL and tfCL e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CLOCK OPERATION
le tPHL tPLH
Propagation Delay Time
Carry Out Line
VDD e 5V
VDD e 10V
VDD e 15V
415
800
ns
160
320
ns
130
250
ns
( Carry Out Line
VDD e 5V
VDD e 10V
VDD e 15V
CL e 15 pF
240
480
ns
85
170
ns
70
140
ns
o Decode Out Lines
VDD e 5V
VDD e 10V
VDD e 15V
500
1000
ns
200
400
ns
160
320
ns
s tTLH tTHL
Transition Time Carry Out
and Decode Out Lines
tTLH
VDD e 5V
VDD e 10V
VDD e 15V
200
360
ns
100
180
ns
80
130
ns
b tTHL
VDD e 5V
VDD e 10V
VDD e 15V
100
200
ns
50
100
ns
40
80
ns
fCL
Maximum Clock Frequency
VDD e 5V
Measured with
10
2
VDD e 10V
Respect to Carry
25
5
( VDD e 15V
Output Line
30
6
MHz
MHz
MHz
O tWL tWH
Minimum Clock
Pulse Width
VDD e 5V
VDD e 10V
VDD e 15V
125
250
ns
45
90
ns
35
70
ns
trCL tfCL
Clock Rise and
Fall Time
VDD e 5V
VDD e 10V
VDD e 15V
20
ms
15
ms
5
ms
tSU
Minimum Clock Inhibit
VDD e 5V
Data Setup Time
VDD e 10V
VDD e 15V
120
240
ns
40
80
ns
32
65
ns
CIN
Average Input Capacitance
5
75
pF
3
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