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BQ2084-V140_14 Datasheet, PDF (4/64 Pages) Texas Instruments – SBS v1.1-COMPLIANT GAS GAUGE FOR USE WITH THE bq29312
bq2084-V140
SLUS664B – JULY 2005 – REVISED AUGUST 2006
OSCILLATOR
VDD = 3 V to 3.6 V, TA = –20°C to 85°C (unless otherwise noted) (TYP: VDD = 3.3 V, TA = 25°C)
PARAMETER
TEST CONDITIONS
MIN
f(eio) Frequency error from 32.768 kHz
f(dio)
f(sio)
f(sxo)
Frequency drift(1)
Start-up time(2)
ROSC = 100k
XCK1 = 12 pF XTAL
ROSC = 100k, TA = 0°C to 50°C
ROSC = 100k
XCK1 = 12 pF XTAL
–2%
–0.25%
–1%
(1) The frequency drift is measured from the trimmed frequency at VDD = 3.3 V, TA = 25°C.
(2) The start-up time is defined as the time it takes for the oscillator output frequency to be ±1%
TYP
0.5%
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MAX
2%
0.25%
1%
200
250
UNIT
µs
ms
DATA FLASH MEMORY CHARACTERISTICS
VDD = 3 V to 3.6 V, TA = –20°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
tDR
Data retention
Flash programming write-cycles
See (1)
See (1)
t(WORDPROG)
I(DDPROG)
Word programming time
Flash-write supply current
See (1)
See (1)
(1) Specified by design. Not production tested.
MIN TYP
10
20k
8
MAX UNIT
Years
Cycles
2 ms
12 mA
REGISTER BACKUP
I(RBI)
V(RBI)
PARAMETER
RBI data-retention input current
RBI data-retention voltage (1)
(1) Specified by design. Not production tested.
TEST CONDITIONS
VRBI > 2 V, VDD < VIT
MIN TYP MAX UNIT
10 100 nA
1.3
V
SMBus TIMING SPECIFICATIONS
VDD = 3 V to 3.6 V, TA = -20°C to 85°C unless otherwise noted
PARAMETER
TEST CONDITIONS
f(SMB)
f(MAS)
t(BUF)
T(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
SMBus operating frequency
SMBus master clock frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
Data hold time
Slave mode, SMBC 50% duty cycle
Master mode, no clock low slave extend
Receive mode
Transmit mode
tSU:DAT)
t(TIMEOUT)
t(LOW)
t(HIGH)
tLOW:SEXT)
tLOW:MEXT
tf
tr
Data setup time
Error signal/detect
Clock low period
Clock high period
Cumulative clock low slave extend time
Cumulative clock low master extend time
Clock/data fall time
Clock/data rise time
See (1)
See (2)
See (3)
See (4)
(VILMAX – 0.15 V) to (VIHMIN + 0.15 V)
0.9 VDD to (VILMAX– 0.15 V)
MIN TYP MAX
10
100
51.2
4.7
4
4.7
4
0
300
250
25
35
4.7
4
50
25
10
300
1000
UNIT
kHz
kHz
µs
µs
µs
µs
ns
ns
ms
µs
µs
ms
ms
ns
ns
(1) The bq2084-V140 times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH) Max. is minimum bus idle time. SMBC = 1 for t > 50 ms causes reset of any transaction involving bq2084-V140 that is in
progress.
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
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