ADC128S102QML-SP_017 Datasheet, PDF (4/30 Pages) Texas Instruments – Radiation Hardened 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D Converter

ADC128S102QML-SP
SNAS411P – AUGUST 2008 – REVISED APRIL 2017
5 Pin Configuration and Functions
NAC Package
16-Pin CFP
Top View
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PIN
NAME
ANALOG I/O
IN0 to IN7
DIGITAL I/O
CS
DIN
DOUT
SCLK
POWER SUPPLY
AGND
DGND
V_A
V_D
CS
1
VA
2
AGND
3
IN0
4
IN1
5
IN2
6
IN3
7
IN4
8
16
SCLK
15
DOUT
14
DIN
13
VD
12
DGND
11
IN7
10
IN6
9
IN5
Not to scale
TYPE
NO.
Pin Functions
DESCRIPTION
4
5
6
7
8
Input
(Analog)
Analog inputs. These signals can range from 0 V to V_REF.
9
10
11
1
Input Chip select. On the falling edge of CS, a conversion process begins. Conversions
(Digital) continue as long as CS is held low.
14
Input Digital data input. The ADC128S102QML-SP's Control Register is loaded through this
(Digital) pin on rising edges of the SCLK pin.
15
Output Digital data output. The output samples are clocked out of this pin on the falling edges
(Digital) of the SCLK pin.
16
Input Digital clock input. The specified performance range of frequencies for this input is 0.8
(Digital) MHz to 16 MHz. This clock directly controls the conversion and readout processes.
3
Ground The ground return for the analog supply and signals.
12
Ground The ground return for the digital supply and signals.
Positive analog supply pin. This voltage is also used as the reference voltage. This
2
Supply pin should be connected to a quiet 2.7 V to 5.25 V source and bypassed to GND with
1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin.
Positive digital supply pin. This pin should be connected to a 2.7 V to V_A supply, and
13
Supply bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of
the power pin.
4
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