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ADC12130 Datasheet, PDF (4/51 Pages) National Semiconductor (TI) – Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
ADC12130, ADC12132, ADC12138
SNAS098G – MARCH 2000 – REVISED MARCH 2013
www.ti.com
Pin Name
CS
DOR
SCLK
CCLK
VREF+
VREF-
PD
VA+
VD+
DGND
AGND
PIN DESCRIPTIONS (continued)
Pin Description
Chip Select input pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data at the DI input
into the address register and brings DO out of TRI-STATE. With CS low, the falling edge of SCLK shifts the data
resulting from the previous ADC conversion out at the DO output, with the exception of the first bit of data. When
CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When
CS is toggled, the falling edge of CS always clocks out the first bit of data. CS should be brought low while SCLK is
low. The falling edge of CS interrupts a conversion in progress and starts the sequence for a new conversion.
When CS is brought low during a conversion, that conversion is prematurely terminated and the data in the output
latches may be corrupted. Therefore, when CS is brought low during a conversion in progress, the data output at
that time should be ignored. CS may also be left continuously low. In this case, it is imperative that the correct
number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is
applied, the device expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC
expects is the same as the digital output word length. This word length can be modified by the data shifted in at the
DO pin. Table 4 details the data required.
Data Output Ready pin. This pin is an active push/pull output which is low when the conversion result is being
shifted out and goes high to signal that all the data has been shifted out.
Serial Data Clock input. The clock applied to this input controls the rate at which the serial data exchange occurs.
The rising edge loads the information at the DI pin into the multiplexer address and mode select shift register. This
address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for the
ADC. With CS low, the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO,
with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the
rising edge of EOC (end of conversion). When CS is toggled, the falling edge of CS always clocks out the first bit of
data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed
1 μs.
Conversion Clock input. The clock applied to this input controls the successive approximation conversion time
interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 μs.
Positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF = VREF+ −
VREF−) is 1.0 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 63 for recommended
bypassing.
The negative analog voltage reference input. In order to maintain accuracy, the voltage at this pin must not go
below GND or exceed VREF+. (See Figure 63).
Power Down pin. When PD is high the ADC is powered down; when PD is low the ADC is powered up, or active.
The ADC takes a maximum of 700 μs to power up after the command is given.
These are the analog and digital power supply pins. VA+ and VD+ are not connected together on the chip. These
pins should be tied to the same supply voltage and bypassed separately (see Figure 63). The operating voltage
range of VA+ and VD+ is 3.0 VDC to 5.5 VDC.
The digital ground pin (see Figure 63).
The analog ground pin (see Figure 63).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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