ADC1175-50 Datasheet, PDF (4/27 Pages) National Semiconductor (TI) – 8-Bit, 50 MSPS, 125 mW A/D Converter

ADC1175-50
SNAS027G – JANUARY 2000 – REVISED APRIL 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS⁽¹⁾ (continued)
Pin
No.
Symbol
Equivalent Circuit
Description
DV_DD
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12
(10)
CLK
12
CMOS/TTL compatible digital clock input. V_IN is sampled on
the falling edge of CLK input.
3 thru 10
(1 thru 8)
D0–D7
11, 13, 14
(9, 11, 12)
DV_DD
2, 24
(22, 24)
DV_SS
15, 18
(13, 16)
AV_DD
20, 21
(18, 19)
AV_SS
DV_SS
DV_DD
D_n
DV_SS
Conversion data digital Output pins. D0 is the LSB, D7 is the
MSB. Valid data is output just after the rising edge of the
CLK input. These pins are in a high impedance mode when
the PD pin is low.
Positive digital supply pin. Connect to a quiet voltage source
of +5V. AV_DD and DV_DD should have a common source and
be separately bypassed with a 10 µF capacitor and a 0.1 µF
ceramic chip capacitor. See POWER SUPPLY
CONSIDERATIONS for more information.
The ground return for the digital supply. AV_SS and DV_SS
should be connected together close to the ADC1175-50.
Positive analog supply pin. Connect to a quiet voltage source
of +5V. AV_DD and DV_DD should have a common source and
be separately bypassed with a 10 µF capacitor and a 0.1 µF
ceramic chip capacitor. See POWER SUPPLY
CONSIDERATIONS for more information.
The ground return for the analog supply. AV_SS and DV_SS
should be connected together close to the ADC1175-50
package.
4
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