9338_11 Datasheet, PDF (4/8 Pages) Texas Instruments – 9338/DM9338 8-Bit Multiple Port Register

Switching Characteristics
V_CC e a5 0V T_A e a25 C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
9338 (MIL)
C_L e 15 pF
DM9338 (COM)
Min
Max
Min
Max
t_PLH
t_PHL
t_PLH
t_PHL
t_PLH
t_PHL
Propagation Delay
B_n or C_n to Z_n
Propagation Delay
D_A to Z_n
Propagation Delay
CP to Z_n
40
13
40
35
18
35
45
25
45
50
25
50
35
18
35
30
13
30
Units
ns
ns
ns
Functional Description
The 9338 8-bit multiple port register can be considered a 1-
bit slice of eight high speed working registers Data can be
written into any one and read from any two of the eight
locations simultaneously Master slave operation eliminates
all race problems associated with simultaneous read write
activity from the same location When the clock input (CP) is
LOW data applied to the data input line (D_A) enters the
selected master This selection is accomplished by coding
the three write input select lines (A0–A2) appropriately
te ^{Data is stored synchronously with the rising edge of the}
clock pulse
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0 – B2 and
C0 – C2) The information enters the slave while the clock is
HIGH and is stored while the clock is LOW If Slave Enable
is LOW (SLE) the slave latches are continuously enabled
le ^{The signals are available on the output pins (ZB and ZC)}
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously The data
flows into the device is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch The eight latches function as masters and store the
Obso ^{input data The two output latches are slaves and hold the}
data during the read operation The state of each slave is
determined by the state of the master selected by its associ-
ated set of read address inputs
The method of parallel expansion is shown in Figure a One
9338 is needed for each bit of the required word length The
read and write input lines should be connected in common
on all of the devices This register configuration provides
two words of n-bits each at one time where n devices are
connected in parallel
Logic Symbol
V_CC e Pin 16
GND e Pin 8
TL F 9794 – 2
FIGURE a Parallel Expansion
3
TL F 9794 – 4