TPS7A85A Datasheet, PDF (39/46 Pages) Texas Instruments – 4-A, High-Accuracy (0.75%), Low-Noise (4.4 uVRMS), LDO Regulator

www.ti.com
TPS7A85A
SBVS313 – JUNE 2017
Input and output capacitors are selected in accordance with External Component Selection. Ceramic
capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the output
are selected.
To satisfy the required start-up time and still maintain low-noise performance, a 100-nF C_NR/SS is selected. This
value is calculated with Equation 16.
t_SS = (V_NR/SS ´ C_NR/SS ) / I_NR/SS
(16)
At the 4-A maximum load, the internal power dissipation is 2 W and corresponds to a 7°C junction temperature
rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient temperature, the
junction temperature is at 62°C. To further minimize noise, a feed-forward capacitance (C_FF) of 10 nF is selected.
8.2.1.3 Application Curves
10
50
Output Current
V_OUT = 0.9 V
V_OUT = 1.2 V
7.5
V_OUT = 1.8 V
25
5
0
2.5
-25
0
-50
0
0.5
1
1.5
2
Time (ms)
Figure 71. Output Load Transient Response
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
0
V_EN
V_OUT, C_NR/SS = 0 nF
V_OUT, C_NR/SS = 10 nF
V_OUT, C_NR/SS = 47 nF
V_OUT, C_NR/SS = 100 nF
5 10 15 20 25 30 35 40 45 50
Time (ms)
Figure 72. Output Start-Up Response
9 Power-Supply Recommendations
The TPS7A85A device is designed to operate from an input voltage supply range from 1.1 V to 6.5 V. If the input
supply is less than 1.4 V, then a bias rail of at least 3 V must be used. The input voltage range provides
adequate headroom for the device to have a regulated output. This input supply must be well-regulated. If the
input supply is noisy, additional input capacitors with low ESR may help improve output noise performance.
10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. The grounding and layout scheme shown in Figure 73 minimizes
inductive parasitics, and as a result, reduces load-current transients, minimizes noise, and increases circuit
stability.
TI recommends a ground reference plane embedded in the PCB itself or located on the bottom side of the PCB
opposite the components. This reference plane serves to ensure accuracy of the output voltage, shield noise,
and behaves similarly to a thermal plane to spread (or sink) heat from the LDO device when connected to the
thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: TPS7A85A
Submit Documentation Feedback
39