SN74V263_09 Datasheet, PDF (39/52 Pages) Texas Instruments – 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
tCLKH
tCLK
tCLKL
RCLK
tLDS
tLDH
tLDH
LD
tENS
tENH
tENH
REN
tA
tA
tA
tA
Q0–Q16
Data In Output Register
PAE Offset (LSB) PAE Offset (MSB)
PAF Offset (LSB)
PAF Offset (MSB)
NOTES: A. OE = low
B. This diagram is based on programming the SN74V293 ×18 bus width. Add one additional cycle to both the PAE offset and PAF
offset for ×9 bus width.
Figure 17. Parallel Read of Programmable Flag Registers (FWFT and Standard Modes)
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