TSC2301_15 Datasheet, PDF (38/94 Pages) Texas Instruments – PROGRAMMABLE TOUCH SCREEN CONTROLLER

TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
www.ti.com
Bit 12 — PCTE
PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows the
user to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manual
control of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] in
the audio control register (bits 7-2 in register 00h, page 2).
PLLO
0
1
Table 27. PLL Control Enable
Description
Allows modification of bits [11:0].
PLL operates as normal, no manual override (default).
Bit [11:8] — PDC3 - PDC0
PLL Predivider Control. This bit controls the predivider to the internal PLL. These bits represent a 4-bit straight
binary number corresponding to the variable P in the PLL control equation discussed later in this section. The
legal range of these bits is 1h to Fh. The default of these bits is Fh.
Bit [7:4] — A3 - A0
A Control. This bit represent a 4-bit straight binary number corresponding to the variable A in the PLL control
equation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.
Bit [3:0] — N3 - N0
N Control. This bit represents a 4-bit straight binary number corresponding to the variable N in the PLL control
equation discussed later in this section. The legal range of these bits is 0h to Fh. The default of these bits is Fh.
When using a nonaudio standard MCLK frequency or crystal that is not covered by any of the automatic PLL
settings in MCLK[1:0], the user must manually configure the TSC2301 PLL to generate the proper clock for the
audio data converters. The proper clock for any sampling rates that are submultiples of 44.1 kHz is 512 x 44.1
kHz = 22.5792 MHz. This frequency is valid for 44.1 kHz, 22.05 kHz, and 11.025 kHz. The proper clock for any
sampling rates that are submultiples of 48 kHz is 512 x 48 kHz = 24.576 MHz. This frequency is valid for 48 kHz,
32 kHz, 24 kHz, 16 kHz, 12 kHz, and 8 kHz. Equation 3 is used to obtain the proper frequency. Since variables
P, N, and A are integers, the exact proper clock frequencies can not always be obtained. However, examples are
provided for common MCLK/crystal frequencies that minimize the error of the PLL output. One constraint is the N
must always be greater than or equal to A. Another constraint is that the output of the MCLK predivider (the
MCLK/P term) should be greater than 1 MHz. P can be any integer from 1 to 15, inclusive. N and A can be any
integer from 0 to 15, inclusive. In some situations, settings outside of these constraints may work, but should be
verified by the user beforehand. Table 28 shows some settings that have been tested and confirmed to work by
TI.
ǒ Ǔ FOUT
+
MCLK
P
(4N
)
3
A)
,
(N
w
A),
MCLK
P
u
1MHz
(3)
MCLK (MHz)
12
13
16
19.2
19.68
3.6869
12
13
16
19.2
Desired
F_out(MHz)
24.576
24.576
24.576
24.576
24.576
22.5792
22.5792
22.5792
22.5792
22.5792
Table 28. PLL Settings
P
A
N
7
7
9
9
7
11
13
12
12
13
10
10
12
9
9
3
7
12
11
10
13
14
13
15
13
11
11
15
9
11
Actual F_out(MHz)
24.57143
24.55556
24.61538
24.61538
24.60000
22.53106
22.54545
22.59524
22.56410
22.61333
% Error
-0.019
-0.083
0.160
0.160
0.097
-0.213
-0.149
0.071
-0.067
0.151
38