TSB41BA3A-EP Datasheet, PDF (38/68 Pages) Texas Instruments – IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

TSB41BA3A-EP
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SGLS253B—OCTOBER 2004—REVISED MAY 2011
PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)
LLC service request (continued)
NOTE:
The TSB41BA3A-EP accepts a bus request with an invalid speed code and processes the bus
request normally. However, during packet transmission for such a request, the TSB41BA3A-EP
ignores any data presented by the LLC and transmits a null packet.
For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 17.
Table 17. Read Register Request
BIT(s)
0
1−3
4−7
8
NAME
Start bit
Request type
Address
Stop bit
DESCRIPTION
Indicates the beginning of the transfer (always 1)
A 100 indicates this is a read register request.
Identifies the address of the PHY register to be read
Indicates the end of the transfer (always 0)
For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 18.
Table 18. Write Register Request
BIT(s)
0
1−3
4−7
8−15
16
NAME
Start bit
Request type
Address
Data
Stop bit
DESCRIPTION
Indicates the beginning of the transfer (always 1)
A 101 indicates this is a write register request.
Identifies the address of the PHY register to be written to
Gives the data that is to be written to the specified register address
Indicates the end of the transfer (always 0)
For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 19.
Table 19. Acceleration Control Request
BIT(s)
0
1−3
4
5
NAME
Start bit
Request type
Control
Stop bIt
DESCRIPTION
Indicates the beginning of the transfer (always 1)
A 110 indicates this is an acceleration control request.
Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0
Indicates the end of the transfer (always 0)
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the
PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then
any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests
if the receive state is asserted while the LLC is sending the request. The LLC can then reissue the request one
clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or
transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears
an isochronous request only when the serial bus has been won.
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