TPS7A85 Datasheet, PDF (38/48 Pages) Texas Instruments – LDO Voltage Regulator

TPS7A85
SBVS267A – JANUARY 2016 – REVISED FEBRUARY 2016
10 Layout
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10.1 Layout Guidelines
10.1.1 Board Layout
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. The grounding and layout scheme shown in Figure 71 minimizes
inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability.
A ground reference plane is also recommended and is either embedded in the PCB itself or located on the
bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output
voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device when
connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal requirements.
10.2 Layout Example
Ground Plane for Thermal Relief and Signal
Ground
To Bias Supply
To Signal Ground
Enable Signal
CBIAS
CNR/SS
10 9 8 7 6
1.6V 11
5 50mV
BIAS ₁₂
NR/SS 13
Thermal Pad
4 ^PG
3 FB
EN 14
2 SNS
IN 15
16 17 18
1
19 20
OUT
RPG
R2
CFF R1
Input Power Plane
Output Power Plane
To PG Pullup Supply
PG Output
To Signal Ground
To Load
CIN
COUT
Power Ground Plane
Vias used for application purposes.
Figure 71. Example Layout
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