SN65DSI83-Q1 Datasheet, PDF (38/51 Pages) Texas Instruments – Automotive Single-Channel MIPI® DSI to Single-Link LVDS Bridge

SN65DSI83-Q1
SLLSEW7 – DECEMBER 2016
www.ti.com
9.2 Typical Application
Figure 49 shows a typical application using the SN65DSI83-Q1 device for a single channel DSI receiver to
interface a single-channel DSI application processor to an LVDS single-link 18 bit-per-pixel panel supporting
1280 × 800 WXGA resolutions at 60 frames per second.
Application
Processor
1.8V
SN65DSI83-Q1 A_Y0N
A_Y 0P
DA0P
DA0N
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
DACP
DACN
SCL
SDA
IRQ
EN
A_Y1N
A_Y 1P
A_Y2N
A_Y 2P
A_CLKN
A_CLKP
A_Y3N
A_Y 3P
ADDR
REFCLK
GND
100Ω
100Ω
100Ω
100Ω
To column driver
To row driver
VCC
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Typical WXGA 18-bpp Panel Application
9.2.1 Design Requirements
Table 34 shows the SN65DSI83-Q1 desgin parameters.
Table 34. Design Parameters
DESIGN PARAMETERS
VCC
Clock source (REFCLK or DSIA_CLK)
REFCKL frequency
DSIA clock frequency
PANEL INFORMATION
Pixel clock (MHz)
Horizontal active (pixels)
Horizontal blanking (pixels)
Vertical active (lines)
Vertical blanking (lines)
Horizontal sync offset (pixels)
Horizontal sync pulse width (pixels)
Vertical sync offset (lines)
Vertical sync pulse width (lines)
EXAMPLE VALUE
1.8 V (±5%)
DSIA_CLK
N/A
500 MHz
83 MHz
1280
384
800
30
64
128
3
7
38
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