SM320C6414-EP Datasheet, PDF (38/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
TERMINAL
NAME
NO.
TYPE ⁽¹⁾
IPD/IPU
(2)
DESCRIPTION
GP15/PRST ⁽⁶⁾
G3
General–purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GP14/PCLK ⁽⁶⁾
F2
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
GP13/PINTA ⁽⁶⁾
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GP12/PGNT ⁽⁶⁾
J3 I/O/Z
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
GP11/PREQ ⁽⁶⁾
F1
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GP10/PCBE3 ⁽⁶⁾
L2
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GP9/PIDSEL ⁽⁶⁾
M3
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
EMIFA (64-bit) Control Signals Common to All Types of Memory⁽⁸⁾⁽⁹⁾
ACE3
ACE2
ACE1
ACE0
L26 O/Z
K23 O/Z
K24 O/Z
K25 O/Z
IPU
IPU ^{EMIFA memory space enables}
• Enabled by bits 28 through 31 of the word address
IPU _{• Only one pin is asserted during any external data access}
IPU
ABE7
T23 O/Z
IPU
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
T24 O/Z
R25 O/Z
R26 O/Z
M25 O/Z
M26 O/Z
L23 O/Z
IPU
IPU ^{EMIFA byte-enable control}
IPU ^{• Decoded from the low–order address bits. The number of address bits or byte enables}
used depends on the width of external memory.
IPU _{• Byte-write enables for most types of memory}
IPU _{• Can be directly connected to SDRAM read and write mask signal (SDQM)}
IPU
ABE0
L24 O/Z
IPU
APDT
M22 O/Z
IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals
EMIFA (64-Bit) — Bus Arbitration
AHOLDA
N22
O
IPU EMIFA hold-request-acknowledge to the host
AHOLD
V23
I
IPU EMIFA hold request from the host
ABUSREQ
P22
O
IPU EMIFA bus request output
EMIFA (64-Bit) — Asynchronous/Synchronous Memory Control
AECLKIN
H25
I
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6
IPD clock) is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKOUT2
J23 O/Z
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided–by–1, –2, or –4.
AECLKOUT1
J26 O/Z
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
AARE/ ASDCAS/
ASADS/ASRE
J25
O/Z
EMIFA asynchronous memory read–enable/SDRAM column–address strobe/programmable
synchronous interface–address strobe or read–enable
IPU ^{• For programmable synchronous interface, the RENEN field in the CE Space Secondary}
Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then
the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the
ASADS/ASRE signal functions as the ASRE signal.
AAOE/ ASDRAS/
ASOE
J24
O/Z
IPU
EMIFA asynchronous memory output–enable/SDRAM row-address strobe/programmable
synchronous interface output–enable
AAWE/ ASDWE/
ASWE
K26
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write–enable
ASDCKE
L25 O/Z
EMIFA SDRAM clock-enable (used for self–refresh mode). (EMIFA module only.)
IPU
• If SDRAM is not in system, ASDCKE can be used as a general–purpose output.
ASOE3
R22 O/Z
IPU EMIFA synchronous memory output–enable for ACE3 (for glueless FIFO interface)
AARDY
L22
I
IPU Asynchronous memory ready input
EMIFA (64–Bit) — Address
(8) These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA
signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic
EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.
(9) To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
38
Device Configurations
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