PGA460-Q1 Datasheet, PDF (38/112 Pages) Texas Instruments – Automotive Ultrasonic Signal Processor and Transducer Driver

PGA460-Q1
SLASEC8 – FEBRUARY 2017
www.ti.com
7.3.6.2.1.6 UART Operations
7.3.6.2.1.6.1 No-Response Operation
The no-response operation on the UART interface is fairly straightforward. The command field specifies the
address and command for the operation, where the subsequent data bytes, if any, are to be stored in the
PGA460-Q1 device. The number of data bytes to be sent is predetermined by the UART command. The last field
in the frame is the checksum field which is generated by the master. Figure 26 shows an example of memory
register write operation (command 10).
Sync field
Command
Field
1^st Data
Field
2^nd Data
Field
Checksum
Field
Write_Cmd
Write_addr
Write Data
chksm[0:7]
(To Slave)
(To Slave)
(To Slave)
(To Slave)
(To Slave)
Inter-Field
Wait Time
(Optional)
Figure 26. UART No-Response Example
NOTE
If a NO-RESPONSE command arrives on the UART interface while another NO-
RESPONSE command is also served or if the PGA460-Q1 device is busy performing
functions, then the previous command is aborted and the new command is served
immediately. This process is particularly important when the PGA460-Q1 device is running
a record interval because of any of the Command0 through Command5 or Command18
through Command23 being previously received while another command is received on the
UART. In this case, the PGA460-Q1 device aborts the previous command and terminates
the current record interval after which it initiates a new command serving cycle.
7.3.6.2.1.6.2 Response Operation (All Except Register Read)
The response operation of the PGA460-Q1 UART interface is initiated with the master sending a response
request. After the response request is received by the PGA460-Q1 device, the UART responds with the proper
data of the command being requested. In a response operation, the master does not generate a checksum Field,
rather it is generated by the PGA460-Q1.
NOTE
Because the data direction changes (master device to PGA460-Q1 followed by PGA460-
Q1 to master device) and because of the amount of processing time required by the
PGA460-Q1 device to respond, a response delay time of 1-bit period occurs between the
response request and the PGA460-Q1 response on the UART.
Figure 27 shows an example of the PGA460-Q1 response operation.
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