LMK04826B_14 Datasheet, PDF (38/104 Pages) Texas Instruments – Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs

LMK04826B, LMK04828B
SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
www.ti.com
5.4.2 DYNAMIC DIGITAL DELAY
Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little
impact to the clock signal. This is accomplished by substituting the regular clock divider with an alternate
divide value for one cycle. This substitution will occur a number of times equal to the value programmed
into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1.
• By programming a larger alternate divider (delay) value, the phase of the adjusted outputs will be
delayed with respect to the other clocks.
• By programming a smaller alternate divider (delay) value, the phase of the adjusted output will
advanced with respect to the other clocks.
The following table shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL
alternate divide setting for delay by one VCO cycle. The clock will output high during the
DCLKoutX_DDLY_CNTH time to permit a continuous output clock. The clock output will be low during the
DCLKoutX_DDLY_CNTL time.
Table 5-3. Recommended DCLKoutX_DDLY_CNTH/_CNTL values for delay by one VCO cycle
Clock Divider
_CNTH
_CNTL
Clock Divider
2
2
3
17
3
3
4
18
4
2
3
19
5
3
3
20
6
3
4
21
7
4
4
22
8
4
5
23
9
5
5
24
10
5
6
25
11
6
6
26
12
6
7
27
13
7
7
28
14
7
8
29
15
8
8
30
16
8
9
31
(1) To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field.
_CNTH
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16 ⁽¹⁾
_CNTL
9
10
10
11
11
12
12
13
13
14
14
15
15
16 ⁽¹⁾
16 ⁽¹⁾
38
FUNCTIONAL DESCRIPTIONS
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links :LMK04826B, LMK04828B