BQ76PL536APAPT Datasheet, PDF (38/60 Pages) Texas Instruments – 3 to 6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for Applications

bq76PL536A
SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012
www.ti.com
[6] (PARITY):
This bit is used to validate the contents of the protected Group3 registers.
0 = Group3 protected register(s) contents are valid.
1 = Group3 protected register(s) contents are invalid. Group3 registers should be
refreshed from OTP or directly written from the host.
[5] (ECC_ERR):
This bit is used to validate the OTP register blocks.
0 = No double-bit errors (a corrected one-bit error may/may not exist)
1 = An uncorrectable error has been detected in the OTP-EPROM register bank.
OTP-EPROM register(s) are not valid.
[4] (FORCE):
This bit asserts the ALERT signal. It can be used to verify correct operation and
connectivity of the ALERT as a part of system self-test.
0 = Deassert ALERT (default)
1 = Assert the ALERT signal.
[3] (TSD):
[2] (SLEEP):
This bit indicates thermal shutdown is active.
0 = Thermal shutdown is inactive (default).
1 = Die temperature has exceeded T_SD.
This bit indicates SLEEP mode was activated. This bit is only set when SLEEP is first
activated; no continuous ALERT or SLEEP status is indicated after the host resets the
bit, even if the IO_CTRL[SLEEP] bit remains true. (See IO_CTRL[] register for details.)
0 = Normal operation
1 = SLEEP mode was activated.
[1] (OT2):
[0] (OT1):
This bit indicates an overtemperature fault has been detected via TS2.
0 = Temperature is lower than or equal to the V_OT2 (or input disabled by
IO_CONTROL[TS2] = 0).
1 = Temperature is higher than V_OT2.
This bit indicates an overtemperature fault has been detected via TS1.
0 = Temperature is lower than or equal to the V_OT1 (or input disabled by
IO_CONTROL[TS1] = 0).
1 = Temperature is higher than V_OT1.
FAULT_STATUS REGISTER (0x21)
7
6
5
4
3
2
1
0
–
–
I_FAULT
FORCE
POR
CRC
CUV
COV
The FAULT_STATUS register provides information about the source of the FAULT signal. The host must clear
each fault flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed
to implement self-test of the IC stack and wiring.
[7] (not implemented)
[6] (not implemented)
[5] (I_FAULT):
The device has failed an internal register consistency check. Measurement data and
protection function status may not be accurate and should not be used.
0 = No internal register consistency check fault exists.
38
Submit Documentation Feedback
Product Folder Links :bq76PL536A
Copyright © 2011–2012, Texas Instruments Incorporated