USBN9604SLBX Datasheet, PDF (37/62 Pages) Texas Instruments – Low EMI, low standby current, 24 MHz oscillator

7.0 Register Set (Continued)
7.1.13 NAK Event Register (NAKEV)
bit 7
bit 6
bit 5
RXFIFO3 RXFIFO2 RXFIFO1
OUT3-0
0
0
0
CoR
bit 4
FIFO0
0
bit 3
bit 2
bit 1
TXFIFO3 TXFIFO2 TXFIFO1
IN3-0
0
0
0
CoR
bit 0
FIFO0
0
IN
Set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Ad-
dress, FAR, register is set to 1 and EP_EN in the Endpoint Control, EPCx, register is set to 1) in response to an IN token.
This bit is cleared when the register is read.
OUT
Set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is
set to 1 and EP_EN in the EPCx register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as
result of an overrun condition. It is cleared when the register is read.
7.1.14 NAK Mask Register (NAKMSK)
When set and the corresponding bit in the NAKEV register is set, the NAK bit in the MAEV register is set. When cleared, the
corresponding bit in the NAKEV register does not cause NAK to be set.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Same Bit Definition as NAKEV Register
0
0
0
0
0
0
0
0
r/w
7.2 TRANSFER REGISTERS
7.2.1 FIFO Warning Event Register (FWEV)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RXFIFO3 RXFIFO2 RXFIFO1
-
TXFIFO3 TXFIFO2 TXFIFO1
-
RXWARN3-1
Reserved
TXWARN3-1
Reserved
0
0
0
-
0
0
0
-
r
r
-
TXWARN
Transmit Warning. Set to 1 when the respective transmit endpoint FIFO reaches the warning limit, as specified by the TFWL
bits of the respective TXCx register, and transmission from the respective endpoint is enabled. This bit is cleared when the
warning condition is cleared by either writing new data to the FIFO when the FIFO is flushed, or when transmission is done,
as indicated by the TX_DONE bit in the TXSx register.
RXWARN
Receive Warning. Set to 1 when the respective receive endpoint FIFO reaches the warning limit, as specified by the RFWL
bits of the respective EPCx register. This bit is cleared when the warning condition is cleared by either reading data from the
FIFO or when the FIFO is flushed.
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