TPS659121_16 Datasheet, PDF (37/145 Pages) Texas Instruments – PMU for Processor Power

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TPS659121, TPS659122
SWCS071B – AUGUST 2012 – REVISED APRIL 2015
6.4 Power State Machine
The Embedded Power Controller (EPC) manages the state of the device and controls the power up
sequence.
The EPC will support the following states:
The transitions for the state machine are shown figure below
• NO SUPPLY: The main battery supply voltage is not high enough to power the LDOAO (LDO always
ON) regulator. A global reset is asserted in this case. Everything on the device is off.
• CONFIG: This state is entered either from NO SUPPLY state automatically or from ACTIVE or SLEEP
when TPS65912x is configured accordingly by Bit LOAD-OTP in [DEVCTRL:Bit6]. When CONFIG is
entered, all registers are set to their default value; nRESPWRON is asserted
• OFF: LDOAO is on and internal logic is active. All power supplies are in off-state. Device can detect
and execute power-up sequence. nRESPWRON is asserted
• ACTIVE: Device POWER ON enable conditions are met and regulated power supplies are ON or can
be enabled with full current capability. Reset is released; interfaces are active
• SLEEP: Device SLEEP enable conditions are met and selected regulated power supplies are in low-
power/OFF mode.
6.5 Transition Conditions
• Device POWER ON enable conditions:
– nPWRON signal low level
– Or PWRHOLD signal high level
– Or Pwr_hold_reg control bit set to 1 (default inactive)
– Or interrupt flag active (default INT1 low) will generate a POWER ON enable condition during a
fixed delay (During this delay it is expected processor to main acknowledge power by writing in
Pwr_Hold reg or setting Power Hold pin to 1). Interrupt sources Generate wake up only if they are
not Mask (OTP/Register dependant)
• Device POWER ON disable conditions:
– nPWRON signal low level during more than the Long Press delay: PWON_LP_DELAY (can be
disable though register programming). The interrupt corresponding to this condition is the
PWRON_LP_IT in INT_STS_REG register.
– Or Die temperature has reached the thermal shutdown threshold (THERM_TS=1)
– Or DEV_OFF_RST control bit set to 1
• Device SLEEP enable condition:
– SLEEP signal low level (Default, or high level depending of the programmed polarity)
– AND DEV_SLP control bit set to 1
– AND interrupt flag inactive (default INT1 high): no none masked interrupt pending
• Device has three different reset scenarios:
– Full reset: all digital of device is reset
• Caused by POR (Power On Reset) when VCCS < UVLO
– General reset:
• Caused by turn-off event with LOAD-OTP=1
• Turn-off event by PWON_LP_OFF_RST bit set to 1
• Optionally for TPS65912x1 by pin PWRON pulled low for longer than 100 ms
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Detailed Description
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