TPS65265 Datasheet, PDF (37/47 Pages) Texas Instruments – Output Current Triple Synchronous Step-Down Converter

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TPS65265
SLVSD86A – DECEMBER 2015 – REVISED DECEMBER 2015
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 V and 17 V. This input power
supply should be well regulated. If the input supply is located more than a few inches from the TPS65265
converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 μF is a typical choice.
11 Layout
11.1 Layout Guidelines
The TPS65265 can be layout on 2-layer PCB, illustrated Figure 74.
Layout is a critical portion of good power supply design. See Figure 74 for a PCB layout example. The top
contains the main power traces for PVIN, VOUT, and LX. Also on the top layer are connections for the remaining
pins of the TPS65265 and a large top side area filled with ground. The top layer ground area should be
connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor and
directly under the TPS65265 device to provide a thermal path from the exposed thermal pad land to ground. The
bottom layer acts as ground plane connecting analog ground and power ground.
For operation at full rated load, the top-side ground area together with the bottom side ground plane must
provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or
voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power
supplies performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low-
ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the
bypass capacitor connections, the PVIN pins, and the ground connections. The PVIN pin must also be bypassed
to ground using a low-ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor should be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components should be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors should be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.
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