MSP430F2132-EP Datasheet, PDF (37/72 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F2132-EP
www.ti.com
SLAS913A – JULY 2013 – REVISED AUGUST 2013
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_USCI
PARAMETER
USCI input clock frequency
CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
f_max,BITCLK
Maximum BITCLK clock frequency
(equals baud rate in MBaud)⁽¹⁾
2.2 V, 3 V
2
MHz
t_τ
UART receive deglitch time⁽²⁾
2.2 V
45 150
ns
3V
45 100
(1) The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 21 and Figure 22)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
t_SU,MI
SOMI input data setup time
2.2 V
110
ns
3V
75
t_HD,MI
SOMI input data hold time
2.2 V
0
ns
3V
0
t_VALID,MO SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2.2 V
3V
30
ns
20
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.
(2) Not ensured for T_A > 105°C.
USCI (SPI Slave Mode)⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 23 and Figure 24)
t_STE,LEAD
t_STE,LAG
t_STE,ACC
t_STE,DIS
PARAMETER
STE lead time, STE low to clock
STE lag time, Last clock to STE high
STE access time, STE low to SOMI data out
STE disable time, STE high to SOMI high
impedance
TEST CONDITIONS
V_CC
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
MIN TYP
50
10
50
50
t_SU,SI
SIMO input data setup time
2.2 V
20
3V
15
t_HD,SI
SIMO input data hold time
2.2 V
10
3V
10
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
2.2 V
75
C_L = 20 pF
3V
50
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(USCI), t_{SU,MI(Master)} + t_{VALID,SO(USCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached slave.
(2) Not ensured for T_A > 105°C.
MAX
UNIT
ns
ns
ns
ns
ns
ns
110
ns
75
Copyright © 2013, Texas Instruments Incorporated
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