DLPC3433 Datasheet, PDF (37/62 Pages) Texas Instruments – Display Controller

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DLPC3433, DLPC3438
DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016
LABB works best when the decision about the strength of gains used is determined by ambient light conditions.
For this reason, there is an option to add an ambient light sensor which can be read by the DLPC343x during
each frame. Based on the sensor readings, LABB will apply higher gains for bright rooms to help overcome any
washing out of images. LABB will apply lower gains in dark rooms to prevent over-punching of images.
8.3.8 94- to 120-Hz 3-D Display Operation
The DLPC343x supports 94- to 120-Hz 3-D display operation, but is limited to:
• Only parallel interfaces (all pixel formats are supported)
• Only non-interlaced image inputs
• 122.4 Hz is maximum supported frame rate
• Un-packed, frame sequential, 3-D format (that is each 100- or 120-Hz source frame contains a single, full
resolution, eye frame separated by VSYNCs, where an eye frame contains image data for a single left or right
eye; not both)
Each DMD frame is displayed at the source frame rate in the order it is received. It is assumed that a front-end
device ahead of the DLPC343x will convert all 3-D sources to the 3-D format defined previously and will provide
any needed left or right eye selection control directly to the DLPC343x 3DR input pin.
8.3.9 DMD (Sub-LVDS) Interface
The DLPC343x ASIC DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum
clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz.
The DLPC343x sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not
all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection,
the DLPC343x also supports a limited number of DMD interface swap configurations that can help board layout
by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 8
shows the four options available for the DLP3010 (.3 720p) DMD specifically.
Table 8. DLP3010 (.3720p) DMD – ASIC to 8-Lane DMD Pin Mapping Options
DLPC343x ASIC 8 LANE DMD ROUTING OPTIONS
OPTION 1
Swap Control = x0
OPTION 2
Swap Control = x2
HS_WDATA_D_P
HS_WDATA_D_N
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_H_P
HS_WDATA_H_N
HS_WDATA_A_P
HS_WDATA_A_N
HS_WDATA_G_P
HS_WDATA_G_N
HS_WDATA_B_P
HS_WDATA_B_N
HS_WDATA_F_P
HS_WDATA_F_N
HS_WDATA_C_P
HS_WDATA_C_N
HS_WDATA_E_P
HS_WDATA_E_N
HS_WDATA_D_P
HS_WDATA_D_N
DMD PINS
Input DATA_p_0
Input DATA_n_0
Input DATA_p_1
Input DATA_n_1
Input DATA_p_2
Input DATA_n_2
Input DATA_p_3
Input DATA_n_3
Input DATA_p_4
Input DATA_n_4
Input DATA_p_5
Input DATA_n_5
Input DATA_p_6
Input DATA_n_6
Input DATA_p_7
Input DATA_n_7
8.3.10 Calibration and Debug Support
The DLPC343x contains a test point output port, TSTPT_(7:0), which provides selected system calibration
support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs
when reset is released. The state of these signals is sampled upon the release of system reset and the captured
value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown
resistor, thus external pullups must be used to modify the default test configuration. The default configuration
(x000) corresponds to the TSTPT_(7:0) outputs remaining tri-stated to reduce switching activity during normal
operation. For maximum flexibility, an option to jumper to an external pullup is recommended for TSTPT_(2:0).
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