DLPC300_15 Datasheet, PDF (37/51 Pages) Texas Instruments – DLP Digital Controller

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System Power-Up and Power-Down Sequence (continued)
DLPC300
DLPS023C – JANUARY 2012 – REVISED AUGUST 2015
An active-high pulse on GPIO 4_INTF following the initialization
period indicates an error condition has been detected. The
source of the error is reported in the system status.
RESET
GPIO 4_INFT
100 ms max
(INIT_BUSY)
(ERR IRQ )
5 ms max
0 ms min
GPIO 4_INTF is driven high within 5 ms
after RESET is released to indicate
Auto-Initialization is busy.
I²C or DBI-C traffic
(SCL, SDA, CSZ)
3 ms min
I²C access to DLPC300 should not start until GPIO 4_INTF
(INIT_BUSY flag) goes low (this should occur within 100 ms
from the release of RESET if the Motor Control function is
not used. If Motor Control is used, this may take several
seconds.)
Figure 18. Initialization Timeline
9.2 System Power I/O State Considerations
Note that:
• If VCC18 I/O power is applied when VDD10 core power is not applied, then all mDDR (non fail-safe) and non-
mDDR (fail-safe) output signals associated with the VCC18 supply are in a high-impedance state.
• If VCC_INTF or VCC_FLSH I/O power is applied when VDD10 core power is not applied, then all output
signals associated with these inactive I/O supplies are in a high-impedance state.
• If VDD10 core power is applied but VCC_INTF or VCC_FLSH I/O power is not applied, then all output signals
associated with these inactive I/O supplies are in a high-impedance state.
• If VDD10 core power is applied but VCC18 I/O power is not applied, then all mDDR (non fail-safe) and non-
mDDR (fail-safe) output signals associated with the VCC18 I/O supply are in a high-impedance state;
however, if driven high externally, only the non-mDDR (fail-safe) output signals remain in a high-impedance
state, and the mDDR (non fail-safe) signals are shorted to ground through clamping diodes.
9.3 Power-Good (PARK) Support
The PARK signal is defined to be an early warning signal that should alert the controller 500 µs before dc supply
voltages have dropped below specifications. This allows the controller time to park the DMD, ensuring the
integrity of future operation. Note that the reference clock should continue to run and RESET should remain
deactivated for at least 500 µs after PARK has been deactivated (set to a logic low) to allow the park operation to
complete.
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