DAC39J84 Datasheet, PDF (37/149 Pages) Texas Instruments – Digital-to-Analog Converter

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DAC39J84
SLASE48A – NOVEMBER 2014 – REVISED JANUARY 2015
SDENB
SCLK
SDIO
SDO
Instruction Cycle
Data Transfer Cycle
rwb
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDENB
SCLK
SDIO
SDO
Data n
Data n-1
td(Data)
Figure 59. Serial Interface Read Timing Diagram
In the SIF interface there are four types of registers:
• NORMAL: The NORMAL register type allows data to be written and read from. All 16-bits of the data are
registered at the same time. There is no synchronizing with an internal clock thus all register writes are
asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
– AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are
used when it is desirable to synchronize the block after writing the register or in the case of a single field
that spans across multiple registers. For instance, the NCO requires three 16-bit register writes to set the
frequency. Upon writing the last of these registers an autosync is generated to deliver the entire field to
the NCO block at once, rather than in pieces after each invidiual register write. For a field that spans
multiple registers, all non-AUTOSYNC registers for the field must be written first before the actual
AUTOSYNC register.
– No RESET Value: These are NORMAL registers, but the reset value cannot be guaranteed. This could
be because the register has some read_only bits or some internal logic partially controls the bit values.
• READ_ONLY: Registers that can be read from but not written to.
• WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written
and read, however, when the internal logic asynchronously sets a bit high in one of these registers, that bit
stays high until it is written to ‘0’. This way interrupts will be captured and stay constant until cleared by the
user. In DAC39J84, register config100-108 are WRTE_TO_CLEAR registers.
7.3.8 Multi-Device Synchronization
In many applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely
synchronized such that their outputs are phase aligned. DAC39J84 achieves the deterministic latency using
SYSREF (JESD204B Subclass 1).
SYSREF is generated from the same clock domain as DACCLK, and is sampled at the rising edges of the device
clock. It can be periodic, single-shot or “gapped” periodic. After having resynchronized its local multiframe clock
(LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the signal on
the SYSREF input can be enabled and disabled via the SPI interface.
7.3.9 Input Multiplexer
The DAC39J84 includes a multiplexer after the JESD204B interface that allows any input stream A-B to be
routed to any signal cannel A-B. See pathx_in_sel for details on how to configure the cross-bar switches.
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