LM3S300 Datasheet, PDF (364/503 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins which default
to the SSI function. The column in the table below titled "Pin Assignment" lists the possible GPIO
pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 241) should be set to choose the SSI function. For more information
on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 223.
Table 11-1. SSI Signals (48QFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSIClk
19
I/O
TTL
SSI clock.
SSIFss
20
I/O
TTL
SSI frame.
SSIRx
21
I
TTL
SSI receive.
SSITx
22
O
TTL
SSI transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
11.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
11.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 1.5 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 383). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 376).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 468 to view SSI timing parameters.
11.3.2 FIFO Operation
11.3.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 380), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit
FIFO is empty and the master initiates, the slave transmits the 8th most recent value in the transmit
FIFO. If less than 8 values have been written to the transmit FIFO since the SSI module clock was
364
July 14, 2014
Texas Instruments-Production Data