TMS320F280049M_17 Datasheet, PDF (36/214 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F280049M
SPRS945 – JANUARY 2017
www.ti.com
4.3.4 Test, JTAG, Voltage Regulator, and Reset
Table 4-5. Test, JTAG, Voltage Regulator, and Reset
SIGNAL NAME
FLT1
FLT2
TCK
TMS
VREGENZ
X1
XRSn
DESCRIPTION
Flash test pin 1. Reserved for TI. Must be left
unconnected.
Flash test pin 2. Reserved for TI. Must be left
unconnected.
JTAG test clock with internal pullup.
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK. This device
does not have a TRSTn pin. An external pullup
resistor (recommended 2.2 kΩ) on the TMS pin to
VDDIO should be placed on the board to keep
JTAG in reset during normal operation.
Internal voltage regulator enable with internal
pulldown. Tie directly to VSS (low) to enable the
internal VREG. Tie directly to VDDIO (high) to use
an external supply.
Crystal oscillator input or single-ended clock input.
The device initialization software must configure
this pin before the crystal oscillator is enabled. To
use this oscillator, a quartz crystal circuit must be
connected to X1 and X2. This pin can also be used
to feed a single-ended 3.3-V level clock.
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven low
by the device. An external circuit may also drive
this pin to assert a device reset. This pin is also
driven low by the MCU when a watchdog reset
occurs. During watchdog reset, the XRSn pin is
driven low for the watchdog reset duration of 512
OSCCLK cycles. A resistor with a value from 2.2
kΩ to 10 kΩ should be placed between XRSn and
VDDIO. If a capacitor is placed between XRSn and
VSS for noise filtering, it should be 100 nF or
smaller. These values allow the watchdog to
properly drive the XRSn pin to VOL within 512
OSCCLK cycles when the watchdog reset is
asserted. The output buffer of this pin is an open-
drain with an internal pullup. If this pin is driven by
an external device, TI recommends using an open-
drain device.
PIN
TYPE
I/O
I/O
I
I
I
I/O
I/OD
GPIO 100 PZ
49
48
60
62
73
69
2
64 PM 64 PMQ 56 RSH
30
29
36
36
33
38
38
35
46
46
42
42
39
3
3
4
36
Terminal Configuration and Functions
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