DLP470NE Datasheet, PDF (36/42 Pages) Texas Instruments – 0.47 1080P DMD

DLP470NE
DLPS091 – AUGUST 2017
10 Layout
www.ti.com
10.1 Layout Guidelines
The DLP470NE DMD is part of a chipset that is controlled by the DLPC4422 display controller in conjunction with
the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the
DLP470NE DMD. The DLP470NE DMD board is a high-speed multi-layer PCB, with primarily high-speed digital
logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals. The remaining traces are comprised of
low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and
VBIAS. Solid planes are required for DMD_P3P3V(3.3V), DMD_P1P8V and Ground. The target impedance for
the PCB is 50 Ω ±10% with the LVDS traces being 100 Ω ±10% differential. TI recommends using an 8 layer
stack-up as described in Table 9.
10.2 Layout Example
10.2.1 Layers
The layer stack-up and copper weight for each layer is shown in Table 9. Small sub-planes are allowed on signal
routing layers to connect components to major sub-planes on top/bottom layers if necessary.
LAYER
NO.
1
2
3
4
5
6
7
8
LAYER NAME
Side A - DMD only
Ground
Signal
Ground
DMD_P3P3V
Signal
Ground
Side B - All other Components
Table 9. Layer Stack-Up
COPPER WT.
(oz.)
1.5
1
0.5
1
1
0.5
1
1.5
COMMENTS
DMD, escapes, low frequency signals, power sub-planes.
Solid ground plane (net GND).
50 Ω and 100 Ω differential signals
Solid ground plane (net GND)
+3.3-V power plane (net DMD_P3P3V)
50 Ω and 100 Ω differential signals
Solid ground plane (net GND).
Discrete components, low frequency signals, power sub-planes
10.2.2 Impedance Requirements
TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed in
Table 10.
Signal Type
C channel LVDS differential pairs
D channel LVDS differential pairs
Table 10. Special Impedance Requirements
Signal Name
DDCP(0:15), DDCN(0:15)
DCLKC_P, DCLKC_N
SCTRL_CP, SCTRL_CN
DDDP(0:15), DDDN(0:15)
DCLKD_P, DCLKD_N
SCTRL_DP, SCTRL_DN
Impedance (ohms)
100 ±10% differential across
each pair
100 ±10% differential across
each pair
10.2.3 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.005” design rule. Minimum trace
clearance from the ground ring around the PWB has a 0.1” minimum. An analysis of impedance and stack-up
requirements determine the actual trace widths and clearances.
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