ADS8354 Datasheet, PDF (36/69 Pages) Texas Instruments – Simultaneous-Sampling, Analog-to-Digital Converters

ADS8354, ADS7854, ADS7254
SBAS556B – OCTOBER 2013 – REVISED AUGUST 2014
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8.5.3 Data Read Operation
The device supports two types of read operations: reading user-programmable registers and reading conversion
results.
8.5.3.1 Reading User-Programmable Registers
The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B.
Figure 89 shows a detailed timing diagram for this operation.
Frame (F)
Frame (F+1)
Frame (F+2)
Frame (F+3)
CS
SCLK
12
N
12345
16
48
12
15 16
47 48
12
N
SDO-A
Valid Data
Valid data as per device configuration.
R15 R14
R1 R0
Valid Data
SDO-B
Valid Data
Valid data as per device configuration.
No change in device
SDI
configuration
B15 B14 B13 B12 X X X
X
Device configuration for frame (F+3)
Note that N is a function of the device configuration, as described in Table 3.
Figure 89. Register Readback Timing
Valid Data
No change in device
configuration
To readback the user-programmable register settings, the appropriate control word should be transmitted to the
device during frame (F+1), as shown in Table 8. Frame (F+1) must have at least 48 SCLK falling edges.
Table 8. Control Word to Readback User-Programmable Registers
USER-PROGRAMMABLE REGISTER
CFR
REFDAC_A
REFDAC_B
CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
B[15:12] (Binary)
B[11:0] (Hex)
0011b
000h
0001b
000h
0010b
000h
Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the
selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 9) and then outputs
0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges.
USER-
PROGRAMMABLE
REGISTER
CFR
REFDAC_A
REFDAC_B
Table 9. Register Data Read Back
DATA READ ON SDO-A IN FRAME (F+2)
R15 R14 R13 R12 R11
—
R3
R2
R1
R0
0
0
1
1 CFG.B11
—
CFG.B3 CFG.B2 CFG.B1 CFG.B0
0
0
0
1 REFDAC_A.D8 — REFDAC_A.D0
0
0
0
0
0
1
0 REFDAC_B.D8 — REFDAC_B.D0
0
0
0
Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
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