LM4F112C4QC Datasheet, PDF (351/1189 Pages) Texas Instruments – Microcontroller

Stellaris^® LM4F112C4QC Microcontroller
Register 77: Micro Direct Memory Access Deep-Sleep Mode Clock Gating
Control (DCGCDMA), offset 0x80C
The DCGCDMA register provides software the capability to enable and disable the μDMA module
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the μDMA module. To support
legacy software, the DCGC2 register is available. A write to the UDMA bit in the DCGC2
register also writes the D0 bit in this register. If the UDMA bit is changed by writing to the
DCGC2 register, it can be read back correctly with a read of the DCGC2 register. If
software uses this register to control the clock for the μDMA module, the write causes
proper operation, but the UDMA bit in the DCGC2 register does not reflect the value of
the D0 bit. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA)
Base 0x400F.E000
Offset 0x80C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
D0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
D0
Type
RO
R/W
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Module Deep-Sleep Mode Clock Gating Control
Value Description
1 Enable and provide a clock to the μDMA module in deep-sleep
mode.
0 μDMA module is disabled.
April 25, 2012
351
Texas Instruments-Advance Information