TPS65023-Q1_16 Datasheet, PDF (35/50 Pages) Texas Instruments – Power Management IC For Li-Ion Powered Systems

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TPS65023-Q1
SLVS927E – MARCH 2009 – REVISED MARCH 2016
At nominal load current, the inductive converters operate in PWM mode. The overall output-voltage ripple is the
sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
DV_OUT
=
V_OUT
´
1-
V_OUT
V_IN
L´ƒ
´
æ
ç
è
8
´
1
C _OUT
´ƒ
+
ESR
ö
÷
ø
where
• the highest output-voltage ripple occurs at the highest input-voltage V_IN
(7)
At light load currents, the converters operate in PSM and the output-voltage ripple is dependent on the output-
capacitor value. The output-voltage ripple is set by the internal comparator delay and the external capacitor. The
typical output-voltage ripple is less than 1% of the nominal output voltage.
9.2.2.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low-ESR input capacitor is
required for best input-voltage filtering and minimizing the interference with other circuits caused by high input-
voltage spikes. Each DC-DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The
input capacitor is increased without any limit for better input-voltage filtering. The VCC pin is separated from the
input for the DC-DC converters. A filter resistor of up to 10R and a 1-μF capacitor are used for decoupling the
VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold, because up to 3 mA
can flow through this resistor into the VCC pin when all converters are running in PWM mode.
Table 13. Possible Capacitors
CAPACITOR
VALUE
22 μF
22 μF
22 μF
22μF
10 μF
10 μF
CASE SIZE
1206
1206
0805
0805
0805
0805
COMPONENT SUPPLIER
TDK C3216X5R0J226M
Taiyo Yuden JMK316BJ226ML
TDK C2012X5R0J226MT
Taiyo Yuden JMK212BJ226MG
Taiyo Yuden JMK212BJ106M
TDK C2012X5R0J106M
COMMENTS
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
9.2.2.4 Output Voltage Selection
The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down
converter. See Table 14 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is
needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 47.
The output voltage of VDCDC1 is set with the I²C interface. If the voltage is changed from the default, using the
DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1
does not change the voltage set with the register.
Table 14. DCDC1, DCDC2, and DCDC3 Default Voltage Levels
PIN
DEFDCDC1
DEFDCDC2
DEFDCDC3
LEVEL
VCC
GND
VCC
GND
VCC
GND
DEFAULT OUTPUT VOLTAGE
1.6 V
1.2 V
3.3 V
1.8 V
3.3 V
1.8 V
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