English
Language : 

TLV320AIC3254_17 Datasheet, PDF (35/53 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec with Embedded miniDSP
www.ti.com
TLV320AIC3254
SLAS549D – SEPTEMBER 2008 – REVISED NOVEMBER 2014
Register Map (continued)
Decimal
PAGE NO. REG. NO.
0
5
0
6
0
7
0
8
0
9-10
0
11
0
12
0
13
0
14
0
15
0
16
0
17
0
18
0
19
0
20
0
21
0
22
0
23
0
24
0
25
0
26
0
27
0
28
0
29
0
30
0
31
0
32
0
33
0
34
0
35
0
36
0
37
0
38
0
39-41
0
42
0
43
0
44
0
45
0
46
0
47
0
48
0
49
0
50-51
0
52
0
53
Table 4. Summary of Register Map (continued)
Hex
PAGE NO. REG. NO.
0x00
0x05
0x00
0x06
0x00
0x07
0x00
0x08
0x00
0x09-0x0A
0x00
0x0B
0x00
0x0C
0x00
0x0D
0x00
0x0E
0x00
0x0F
0x00
0x10
0x00
0x11
0x00
0x12
0x00
0x13
0x00
0x14
0x00
0x15
0x00
0x16
0x00
0x17
0x00
0x18
0x00
0x19
0x00
0x1A
0x00
0x1B
0x00
0x1C
0x00
0x1D
0x00
0x1E
0x00
0x1F
0x00
0x20
0x00
0x21
0x00
0x22
0x00
0x23
0x00
0x24
0x00
0x25
0x00
0x26
0x00
0x27-0x29
0x00
0x2A
0x00
0x2B
0x00
0x2C
0x00
0x2D
0x00
0x2E
0x00
0x2F
0x00
0x30
0x00
0x31
0x00
0x32-0x33
0x00
0x34
0x00
0x35
DESCRIPTION
Clock Setting Register 2, PLL P and R Values
Clock Setting Register 3, PLL J Values
Clock Setting Register 4, PLL D Values (MSB)
Clock Setting Register 5, PLL D Values (LSB)
Reserved Register
Clock Setting Register 6, NDAC Values
Clock Setting Register 7, MDAC Values
DAC OSR Setting Register 1, MSB Value
DAC OSR Setting Register 2, LSB Value
miniDSP_D Instruction Control Register 1
miniDSP_D Instruction Control Register 2
miniDSP_D Interpolation Factor Setting Register
Clock Setting Register 8, NADC Values
Clock Setting Register 9, MADC Values
ADC Oversampling (AOSR) Register
miniDSP_A Instruction Control Register 1
miniDSP_A Instruction Control Register 2
miniDSP_A Decimation Factor Setting Register
Reserved Register
Clock Setting Register 10, Multiplexers
Clock Setting Register 11, CLKOUT M divider value
Audio Interface Setting Register 1
Audio Interface Setting Register 2, Data offset setting
Audio Interface Setting Register 3
Clock Setting Register 12, BCLK N Divider
Audio Interface Setting Register 4, Secondary Audio Interface
Audio Interface Setting Register 5
Audio Interface Setting Register 6
Digital Interface Misc. Setting Register
Reserved Register
ADC Flag Register
DAC Flag Register 1
DAC Flag Register 2
Reserved Register
Sticky Flag Register 1
Interrupt Flag Register 1
Sticky Flag Register 2
Sticky Flag Register 3
Interrupt Flag Register 2
Interrupt Flag Register 3
INT1 Interrupt Control Register
INT2 Interrupt Control Register
Reserved Register
GPIO/MFP5 Control Register
DOUT/MFP2 Function Control Register
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3254
Submit Documentation Feedback
35