DIX4192-Q1_17 Datasheet, PDF (35/69 Pages) Texas Instruments – Integrated Digital Audio Interface Receiver and Transmitter

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7 (MSB)
0
RXCKOE
RXCKOD[1:0]
RXAMLL
LOL
7 (MSB)
P3
7 (MSB)
J1
DIX4192-Q1
SBFS041A – JULY 2016 – REVISED APRIL 2017
Figure 36. Register 0E: Receiver Control Register 2
6
5
4
3
2
1
0
0
LOL
RXAMLL
RXCKOD1
RXCKOD0
Table 17. Register 0E: Receiver Control Register 2 Field Descriptions
0 (LSB)
RXCKOE
RXCKOE Output Enable
This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance
state.
RXCKOE
RXCKO Output State
0
Disabled; the RXCKO output is set to high-impedance. (default)
1
Enabled; the recovered master clock is available at RXCKO.
RXCKO Output Clock Divider
These bits are used to set the clock divider at the output of PLL2. The output of the divider is the RXCKO clock, available internally or at
the RXCKO output (pin 12).
RXCKOD1
RXCKOD0
RXCKO Output Divider
0
0
Passthrough; no division is performed. (default)
0
1
Divide the PLL2 clock output by 2.
1
0
Divide the PLL2 clock output by 4.
1
1
Divide the PLL2 clock output by 8.
Receiver Automatic Mute for Loss of Lock
This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2.
RXAMLL
Receiver Auto-Mute Function
0
Disabled (default)
1
Enabled; audio data output from the DIR block is forced low for a loss of lock condition.
Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2)
This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs.
LOL
Receiver PLL2 Operation
0
The PLL2 output clock is stopped for a loss of lock condition. (default)
1
The PLL2 output clock free runs when a loss of lock condition occurs.
Figure 37. Register 0F: Receiver PLL1 Configuration Register 1
6
5
4
3
2
1
P2
P1
P0
J5
J4
J3
0 (LSB)
J2
Figure 38. Register 10: Receiver PLL1 Configuration Register 2
6
5
4
3
2
1
J0
D13
D12
D11
D10
D9
0 (LSB)
D8
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