ADS8578S Datasheet, PDF (35/58 Pages) Texas Instruments – 14-Bit, High-Speed, 8-Channel, Simultaneous-Sampling ADC with Bipolar Inputs on a Single Supply

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ADS8578S
SBAS825 – APRIL 2017
Device Functional Modes (continued)
8.4.1.5 CONVSTA, CONVSTB (Input)
Conversion start A (CONVSTA) and conversion start B (CONVSTB) are active-high, conversion control digital
input signals. CONVSTA can be used to simultaneously sample and initiate the conversion process for the first
half count of device input channels (channels 1-4 for the ADS8578S), whereas CONVSTB can be used to
simultaneously sample and initiate the conversion process for the latter half count of device input channels
(channels 5-8 for the ADS8578S). For simultaneous sampling of all input channels, both pins can be shorted
together and a single CONVST signal can be used to control the conversion on all input channels. However, in
the oversampling mode of operation (see the Oversampling Mode of Operation section), both the CONVSTA and
CONVSTB signals must be tied together.
On the rising edge of the CONVSTA, CONVSTB signals, the internal track-and-hold circuits for each analog input
channel are placed into hold mode and the sampled input signal is converted using an internal clock. The
CONVSTA, CONVSTB signals can be pulled low when the internal conversion is over, as indicated by the BUSY
signal (see the BUSY (Output) section). At this point, the front-end circuit for all analog input channels acquires
the respective input signals and the internal ADC is not converting. The output data can be read from the device
irrespective of the status of the CONVSTA, CONVSTB pins, as there is no degradation in device performance,
as explained in the Data Read Operation section.
8.4.1.6 RESET (Input)
The RESET pin is an active-high digital input. A dedicated reset pin allows the device to be reset at any time in
an asynchronous manner. All digital circuitry in the device is reset when the RESET pin is set to logic high and
this condition remains active until the pin returns low. The device must always be reset after power-up as well as
after recovery from shut-down mode when all the supplies and references have settled to the required accuracy.
If the RESET is issued during an ongoing conversion process, then the device aborts the conversion and output
data is invalid. If the reset signal is applied during a data read operation, then the output data registers are all
reset to zero.
In order to initiate the next conversion cycle after deactivating a reset condition, allow for a minimum time delay
between the falling edge of the RESET input and the rising edge of the CONVSTA, CONVSTB inputs (see the
Timing Requirements: CONVST Control table). Any violation in this timing requirement can result in corrupting
the results from the next conversion.
8.4.1.7 RD/SCLK (Input)
RD/SCLK is a dual-function pin. Table 3 explains the usage of this pin under different operating conditions of the
device.
Table 3. RD/SCLK Pin Functionality
DEVICE OPERATING CONDITION
Parallel interface
PAR/SER/BYTE SEL = 0
DB15/BYTE SEL = 0
Parallel byte interface
PAR/SER/BYTE SEL = 1
DB15/BYTE SEL = 1
Serial interface
PAR/SER/BYTE SEL = 1
DB15/BYTE SEL = 0
FUNCTIONALITY OF THE RD/SCLK INPUT
Functions as an active-low digital input pin to read the output data from the device.
In parallel or parallel byte interface mode, the output bus is enabled when both the
CS and RD inputs are tied to a logic low input (see the Data Read Operation
section).
Functions as an external clock input for the serial data interface. In serial mode, all
synchronous accesses to the device are timed with respect to the rising edge of
the SCLK signal (see the Serial Data Read section).
8.4.1.8 CS (Input)
The CS pin indicates an active-low, chip-select signal. A rising edge on the CS signal outputs all data lines in tri-
state mode. This function allows multiple devices to share the same output data lines. The falling edge of the CS
signal marks the beginning of the output data transfer frame in any interface mode of operation for the device. In
the parallel and parallel byte interface modes, both the CS and RD input pins must be driven low to enable the
digital output bus for reading the conversion data (DB[15:0] for parallel and DB[7:0] for parallel byte interface). In
serial mode, the falling edge of the CS signal takes the DOUTA, DOUTB serial data output lines out of tri-state
mode and outputs the MSB of the previous conversion result.
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