TSB41BA3B_16 Datasheet, PDF (34/68 Pages) Texas Instruments – IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

TSB41BA3B
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS678 − SEPTEMBER 2005
APPLICATION INFORMATION
crystal selection (continued)
C9
C10
X1
Figure 11. Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for the design be to measure the frequency of
the PCLK output of the PHY. This should be done using a frequency counter with an accuracy of six digits or
better. If the PCLK frequency is more than the crystal’s tolerance from 49.152 MHz or 98.304 MHz, then the
load capacitance of the crystal can be varied to improve frequency accuracy. If the frequency is too high, add
more load capacitance; if the frequency is too low, decrease the load capacitance. Typically, changes must be
done to both load capacitors (C9 and C10 in Figure 11) at the same time, and both must be of the same value.
Additional design details and requirements can be provided by the crystal vendor.
bus reset
It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the
initiate-short-bus-reset (ISBR) bit (bit 1, PHY register 0101b). Care must be taken to not change the value of
any of the other writeable bits in this register when the ISBR bit is written to.
In the TSB41BA3B, the initiate-bus-reset (IBR) bit can be set to 1 in order to initiate a bus reset and initialization
sequence; however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY register 1 along
with the root-holdoff bit (RHB) and gap-count register. As required by the 1394b Supplement, this configuration
maintains compatibility with older Texas Instruments PHY designs which were based on either the suggested
register set defined in Annex J of IEEE Std 1394-1995 or the 1394a-2000 Supplement. Therefore, whenever
the IBR bit is written, the RHB and gap-count register are also necessarily written.
It is recommended that the RHB and gap-count register only be updated by PHY configuration packets. The
TSB41BA3B is 1394a- and 1394b-compliant, and therefore, both the reception and transmission of PHY
configuration packets cause the RHB and gap-count register to be loaded, unlike older IEEE Std
1394-1995-compliant PHYs which decode only received PHY configuration packets.
The gap-count register is set to the maximum value of 63 after two consecutive bus resets without an intervening
write to the gap-count register, either by a write to PHY register 1 or by a PHY configuration packet. This
mechanism allows a PHY configuration packet to be transmitted and then a bus reset to be initiated so as to
verify that all nodes on the bus have updated their RHBs and gap-count register values, without having the
gap-count register set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which
initiates a bus reset, then causes the gap-count register of each node to be set to 63. Note, however, that if a
subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, then all other nodes on the
bus have their gap-count register values set to 63, while this node’s gap-count register remains set to the value
just loaded by the write to PHY register 1.
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