TPA3250 Datasheet, PDF (34/41 Pages) Texas Instruments – 130W peak PurePath Ultra-HD Pad Down Class-D Amplifier

TPA3250
SLASE99A – DECEMBER 2015 – REVISED APRIL 2016
12.2 Layout Examples
12.2.1 BTL Application Printed Circuit Board Layout Example
Pad to top layer ground pour
Bottom Layer Signal Traces
Top Layer Signal Traces
Bottom to top layer connection via
System Processor
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A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors placed close to the pins.
D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour
Figure 32. BTL Application Printed Circuit Board - Composite
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