TUSB3200A_16 Datasheet, PDF (33/102 Pages) Texas Instruments – USB Streaming Controller (STC)

TUSB3200A
www.ti.com
SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011
buffer overflow occurs, the DMA will set the overflow bit in the endpoint configuration byte.
4. The host PC sends an in token packet addressed to the in endpoint. The UBM reads the X (or Y)
buffer data count byte to verify the NACK bit is cleared and to obtain the sample count of the new data
packet. The UBM reads the data packet from the X (or Y) endpoint buffer then transmits the data to the
PC. At the end of the USB transaction, the UBM sets the X (or Y) buffer NACK bit to a 1. Note that if a
new data packet has not been written to the buffer by the DMA, then the NACK bit will still be set to a
1 and the UBM will send a null packet to the PC. Also, note that there is no endpoint interrupt
generated for isochronous endpoints.
2.2.7.4.4 Isochronous In Transaction (MCU as source and host PC as destination)
The steps to be followed for an isochronous in transaction are as follows:
1. MCU initializes one of the in endpoints as an in isochronous endpoint by programming the appropriate
USB endpoint configuration block. This entails programming the buffer size and the buffer base
address for both the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint
bit, enabling the endpoint, and setting the NACK bit.
2. The host PC sends an in token packet addressed to the in endpoint. The UBM reads the X (or Y)
buffer data count byte to verify the NACK bit is cleared and to obtain the sample count of the new data
packet. The UBM reads the data packet from the X (or Y) endpoint buffer then transmits the data to the
PC. At the end of the USB transaction, the UBM sets the X (or Y) buffer NACK bit to a 1. Note that if a
new data packet has not been written to the buffer by the MCU then the NACK bit will still be set to a 1
and the UBM will send a null packet to the PC. Also, note that there is no endpoint interrupt generated
for isochronous endpoints.
2.2.8 Adaptive Clock Generator (ACG)
The adaptive clock generator is used to generate a programmable master clock output signal (MCLKO)
that can be used by the codec port interface and the codec device. The ACG can be used to generate the
master clock for the codec for USB asynchronous, synchronous, and adaptive modes of operation.
However, for the USB asynchronous mode of operation, an external clock can be used to drive the MCLKI
signal of the TUSB3200A. In this scenario, the MCLKI signal would be used as the clock source for the
codec port interface instead of the clock output from the ACG.
A block diagram of the adaptive clock generator is shown in Figure 2-1. The frequency synthesizer circuit
generates a programmable clock with a frequency range of 12 to 25 MHz. The output of the frequency
synthesizer feeds the divide-by-M circuit, which can be programmed to divide by 1 to 16. As a result, the
frequency range of the MCLKO signal is 750 kHz to 25 MHz. The duty cycle of the MCLKO signal is 50%
for all programmable MCLKO frequencies.
6 MHz
Oscillator
MCLKI
MCLKI2
Capture Counter
Mux
PLL
Frequency
Synthesizer
Divide
by M
Mux
Divide
by I
MCLKO
MCLKO2
Mux
Divide
by B
CSCLK
Figure 2-1. Adaptive Clock Generator
The ACG is controller by the following registers. See Section A.5.3 for details.
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