OPA4830 Datasheet, PDF (33/45 Pages) National Semiconductor (TI) – Quad, Low-Power, Single-Supply, Wideband Operational Amplifier

OPA4830
www.ti.com.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and thus influences the bandwidth. For the example
in Figure 88, the R_M value combines in parallel with
the external 50Ω source impedance (at high
frequencies), yielding an effective driving impedance
of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in
series with R_G for calculating the noise gain. The
resulting noise gain is 2.87 for Figure 88, as opposed
to only 2 if R_M could be eliminated as discussed
above. The bandwidth is therefore lower for the gain
of –2 circuit of Figure 88 (NG = +2.87) than for the
gain of +2 circuit of Figure 72.
The third important consideration in inverting amplifier
design is setting the bias current cancellation
resistors on the noninverting input (a parallel
combination of R_T = 750Ω). If this resistor is set equal
to the total dc resistance looking out of the inverting
node, the output dc error (as a result of the input bias
currents) is reduced to (input offset current) times R_F.
With the dc blocking capacitor in series with R_G, the
dc source impedance looking out of the inverting
mode is simply R_F = 750Ω for Figure 88. To reduce
the additional high-frequency noise introduced by this
resistor and power-supply feed-through, R_T is
bypassed with a capacitor.
OUTPUT CURRENT AND VOLTAGES
The OPA4830 provides outstanding output voltage
capability. For the +5V supply, under no-load
conditions at +25°C, the output voltage typically
swings closer than 90mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at
cold startup does the output current and voltage
decrease to the numbers shown in the specification
tables. As the output transistors deliver power, the
junction temperatures increase, decreasing the V_BEs
(increasing the available output voltage swing), and
increasing the current gains (increasing the available
output current). In steady-state operation, the
available output voltage and current is always greater
than that shown in the over-temperature
specifications, because the output stage junction
temperatures are higher than the minimum specified
operating ambient temperature.
To maintain maximum output stage linearity, no
output short-circuit protection is provided. This
absence of protection is not normally a problem,
because most applications include a series matching
resistor at the output that limits the internal power
dissipation if the output side of this resistor is shorted
to ground. However, shorting the output pin directly to
the adjacent positive power-supply pin (8-pin
packages), in most cases, destroys the amplifier. If
additional short-circuit protection is required, consider
a small series resistor in the power-supply leads. This
resistor reduces the available output voltage swing
under heavy output loads.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance that
may be recommended to improve ADC linearity. A
high-speed, high open-loop gain amplifier such as the
OPA4830 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load.
The Typical Characteristics show the recommended
R_S versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads
greater than 2pF can begin to degrade the
performance of the OPA4830. Long PCB traces,
unmatched cables, and connections to multiple
devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the output pin (see the Board Layout Guidelines
section).
The criterion for setting this R_S resistor is a maximum
bandwidth, flat frequency response at the load. For a
gain of +2, the frequency response at the output pin
is already slightly peaked without the capacitive load,
requiring relatively high values of R_S to flatten the
response at the load. Increasing the noise gain also
reduces the peaking (see Figure 78).
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