INA209_17 Datasheet, PDF (33/50 Pages) Texas Instruments – High-Side Measurement, Bi-Directional Current/Power Monitor with I2C Interface

INA209
www.ti.com ......................................................................................................................................................... SBOS403B – JUNE 2007 – REVISED MARCH 2009
BIT #
BIT
NAME
POR
VALUE
D15
D14
MWOV MWUV
0
0
SMBus Alert Mask/Enable Control Register 02h (Read/Write)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
MWP MWS+ MWS– MOLOV MOLUV MOLP MCRIT+ MCRIT– MCNVR
—
SMAEN CREN
0
0
0
0
0
0
0
0
0
0
0
0
D1
D0
OLEN WRNEN
0
0
Bits D5–D15 of the SMBus Alert Mask Register mask correspond to bits D5 to D15 of the Status Register to
prevent them from initiating an SMBus Alert. It does not prevent the Status Register bit from setting. Writing a '0'
to an SMBus Alert Mask bit masks it from activating the SMBus Alert. All default values are '0'.
MWOV:
Bit 15
MWUV:
Bit 14
MWP:
Bit 13
MWS+:
Bit 12
MWS–:
Bit 11
MOLOV:
Bit 10
MOLUV:
Bit 9
MOLP:
Bit 8
MCRIT+:
Bit 7
MCRIT–:
Bit 6
MCNVR:
Bit 5
SMAEN:
Bit 3
CREN:
Bit 2
OLEN:
Bit 1
WRNEN:
Bit 0
Bit Descriptions
Warning Bus Over-Voltage Mask
When set to '0', this bit masks the WOV bit of the Status Register.
Warning Bus Under-Voltage Mask
When set to '0', this bit masks the WUV bit of the Status Register.
Warning Power Mask
When set to '0', this bit masks the WP bit of the Status Register.
Warning Shunt Positive Voltage Mask
When set to '0', this bit masks the WS+ bit of the Status Register.
Warning Shunt Negative Voltage Mask
When set to '0', this bit masks the WS– bit of the Status Register.
Over-Limit Bus Over-Voltage Mask
When set to '0', this bit masks the OLOV bit of the Status Register.
Over-Limit Bus Under-Voltage Mask
When set to '0', this bit masks the OLUV bit of the Status Register.
Over-Limit Power Mask
When set to '0', this bit masks the OLP bit of the Status Register.
Critical Shunt Positive Voltage Mask
When set to '0', this bit masks the CRIT+ bit of the Status Register.
Critical Shunt Negative Voltage Mask
When set to '0', this bit masks the CRIT– bit of the Status Register.
Conversion Ready Mask
When set to '0', this bit masks the CNVR bit of the Status Register.
SMBus Alert Enable
1 = Enable SMBus Alert
0 = Disable SMBus Alert (default)
Critical DAC Enable
Enables/disables operation of the Critical pin output.
1 = Enabled
0 = Disabled (default)
Over-Limit Enable
Enables/disables operation of the Overlimit pin output.
1 = Enabled
0 = Disabled (default)
Warning Enable
Enables/disables operation of the Warning pin output.
1 = Enabled
0 = Disabled (default)
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