TPS25740B Datasheet, PDF (32/61 Pages) Texas Instruments – USB Type-C and USB PD Source Controller

TPS25740B
SLVSDR6 – JUNE 2017
www.ti.com
Power Supply
R_S
V_BUS
V_{(VBUS_TH)}
+
-
GDNG
Control
V_I(TRIP)
+
+
-
-
Enable OCP
Deglitch
t_OCP
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Overcurrent Protection Circuit, (ISNS, VBUS)
8.3.9.3 System Fault Input (GD, VPWR)
The gate-driver disable pin provides a method of overriding the internal control of GDNG and GDNS. A falling
edge on GD disables the gate driver within t_GDoff. If GD is held low after a sink is attached for 600 ms then a hard
reset will be generated and the device sends a hard reset and go through its startup process again.
The GD input can be controlled by a voltage or current source. An internal voltage clamp is provided to limit the
input voltage in current source applications. The clamp can safely conduct up to 80 µA and will remain high
impedance up to 6.5 V before clamping.
V_{(GD_TH)}
V_(GDC)
GDNG
Control
Deglitch
t_GDoff
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Overcurrent Protection Circuit, (GD)
If the VPWR pin remains below its falling UVLO threshold (V_{(VPWR_TH)}) for more than 600 ms after a sink is
attached then the devices consider it a fault and will not enable GDNG. If the VPWR pin is between the rising
and falling UVLO threshold, the device may enable GDNG and proceed with normal operations. However, after
GDNG is enabled, if the VBUS pin does not rise above its UVLO within 190 ms the devices consider it a fast-
shutdown fault and disables GDNG. Therefore, in order to ensure USB Type-C compliance and normal
operation, the VPWR pin must be above its rising UVLO threshold (V_{(VPWR_TH)}) within 275 ms of when ENSRC is
pulled low and the VBUS pin must be above V_{(VBUS_RTH)} within 190 ms of GDNG being enabled.
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