SRC4184_08 Datasheet, PDF (32/43 Pages) Texas Instruments – 4-Channel, Asynchronous Sample Rate Converter

SRC4184
SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
www.ti.com
Register 4. Digital Output Attenuation Register—Left Channel
D7
D0
(MSB)
D6
D5
D4
D3
D2
D1
(LSB)
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
This register is utilized to program the digital output attenuation for the Left output channel of the
corresponding SRC section.
Register defaults to 00h, or 0dB (unity gain).
Output Attenuation (dB) = −N × 0.5, where N = AL[7:0]_DEC
Register 5. Digital Output Attenuation Register—Right Channel
D7
(MSB)
D6
D5
D4
D3
D2
AR7
AR6
AR5
AR4
AR3
AR2
D0
D1
(LSB)
AR1
AR0
This register is utilized to program the digital output attenuation for the Right output channel of the
corresponding SRC section. When the TRACK bit in Control Register 1 is set to 1, the Left Channel
attenuation setting will also be used to set the Right Channel attenuation.
Register defaults to 00h, or 0dB (unity gain).
Output Attenuation (dB) = −N × 0.5, where N = AR[7:0]_DEC
Register 6. Sampling Ratio (read only)
D7
(MSB)
SRI4
D6
SRI3
D5
SRI2
D4
SRI1
D3
SRI0
D2
SRF10
D1
SRF9
D0
(LSB)
SRF8
Register 7. Sampling Ratio (read only)
D7
(MSB)
SRF7
D6
SRF6
D5
SRF5
D4
SRF4
D3
SRF3
D2
SRF2
D1
SRF1
D0
(LSB)
SRF0
The contents of Register 6 and Register 7 indicate the input-to-output sampling ratio, and can be used to
determine either the input or output sampling rates when one of the two rates is known.
Bits SRI[4:0] comprise the integer portion of the input-to-output sampling ratio.
Bits SRF[10:0] comprise the fractional portion of the input-to-output sampling ratio.
The contents of Register 6 and Register 7 are updated when Register 6 is read. Register 6 must always be
read first in order to obtain the latest ratio data for both registers.
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