DP83848Q-Q1 Datasheet, PDF (32/82 Pages) Texas Instruments – MII Serial Management Interface

DP83848Q-Q1
SNLS341C – MARCH 2011 – REVISED MARCH 2015
www.ti.com
The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the
FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). Table 5-
3 indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet
size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock)
have the same accuracy.
Table 5-3. Supported Packet Sizes at ±50 ppm ±k100 ppm For Each Clock
Start Threshold RBR[1:0]
1 (4-bits)
2 (8-bits)
3 (12-bits)
0 (16-bits)
Latency Tolerance
2 bits
6 bits
10 bits
14 bits
Recommended Packet Size
at ±50ppm
2,400 bytes
7,200 bytes
12,000 bytes
16,800 bytes
Recommended Packet Size
at ±100ppm
1,200 bytes
3,600 bytes
6,000 bytes
8,400 bytes
5.4.3 802.3u MII Serial Management Interface
5.4.3.1 Serial Management Register Access
The serial management MII specification defines a set of thirty-two 16-bit status and control registers that
are accessible through the management interface pins MDC and MDIO. The DP83848Q-Q1 implements
all the required MII registers as well as several optional registers. These registers are fully described in
Section 5.6.
5.4.3.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data
Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is
bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 5-
4.
MII Management Serial Protocol
Read Operation
Write Operation
Table 5-4. Typical MDIO Frame Format
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.
In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous
logic ones on MDIO to provide the DP83848Q-Q1 with a sequence that can be used to establish
synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time
32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device
if an invalid start, opcode, or turnaround bit is detected.
The DP83848Q-Q1 waits until it has received this preamble sequence before responding to any other
transaction. Once the DP83848Q-Q1 serial management port has been initialized no further preamble
sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit
has occurred.
The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle
line state.
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Detailed Description
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