ADS5525_14 Datasheet, PDF (32/59 Pages) Texas Instruments – 12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS5525
SLWS191B – JULY 2006 – REVISED MAY 2007
APPLICATION INFORMATION
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THEORY OF OPERATION
ADS5525 is a low power 12-bit 170 MSPS pipeline ADC in a CMOS process. ADS5525 is based on switched
capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of
the external input clock. Once the signal is captured by the input sample and hold, the input sample is
sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction
logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14
clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset
binary or binary 2’s complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in
Figure 41.
This differential topology results in good ac-performance even for high input frequencies at high sampling rates.
The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM
pin 13. For a full-scale differential input, each input pin (INP, INM) has to swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2-V_PP differential input swing. The maximum swing is determined by the
internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).
Sampling
Switch
Lpkg
6 nH
R-C-R Filter
Sampling
Capacitor
INP
Cbond
25 W
2 pF
Resr
50 W
200 W
4 pF
Cpar2
1 pF
Ron
15 W
Cpar1
0.8 pF
Csamp
3.2 pF
Ron
10 W
Lpkg
6 nH
25 W
50 W
Ron
15 W
Csamp
3.2 pF
INM
Cbond
2 pF
Resr
Cpar2
1 pF
Sampling
Capacitor
200 W
Sampling
Switch
Figure 41. Input Stage
The input sampling circuit has a 3-dB bandwidth that extends up to 500 MHz, see Figure 42 (measured from the
input pins to the voltage across the sampling capacitors).
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