TLV2548-EP Datasheet, PDF (31/38 Pages) Texas Instruments – 3.0-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTOPOWER-DOWN

TLV2548-EP
www.ti.com
SLAS668 – OCTOBER 2009
requires longer input data hold time.
3. For earlier silicon, the delay time is specified as:
MIN NOM MAX UNIT
SDO = 0 pF
16
Delay time, delay from SCLK falling edge (FS is
V_CC = 4.5 V
SDO = 100 pF
20
active) or SDO = 100 pF 20 ns SCLK rising edge
ns
(FS = 1) to next SDO valid, t_d(SCLK-DOV).
SDO = 0 pF
24
V_CC = 2.7 V
SDO = 100 pF
30
This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time
required by the external digital host processor, therefore, a minimum value is specified. The newer silicon
has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK
exists as the hold time for the external host processor, the specified maximum value helps with the
calculation of the setup time requirement of the external digital host processor.
For an explanation of the DSP mode, reverse the rising/falling edges in item 2. above.
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