RM48L930_15 Datasheet, PDF (31/172 Pages) Texas Instruments – RM48Lx30 16- and 32-Bit RISC Flash Microcontroller

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RM48L930, RM48L730, RM48L530
SPNS176C – APRIL 2012 – REVISED JUNE 2015
4.3.2.11 External Memory Interface (EMIF)
EMIF_CKE
Table 4-30. External Memory Interface (EMIF)
TERMINAL
SIGNAL NAME
337
ZWT
L3
SIGNAL
TYPE
Output
RESET
PULL
STATE
PULL TYPE
None
EMIF_CLK
Pulldown
K3
I/O
None
ETMDATA[13]/EMIF_nOE
EMIF_nWAIT
EMIF_nWE
EMIF_nCAS
EMIF_nRAS
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]
EMIF_nCS[2]
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]
EMIF_nCS[4]/RTP_DATA[7]
ETMDATA[15]/EMIF_nDQM[0]
ETMDATA[14]/EMIF_nDQM[1]
ETMDATA[12]/EMIF_BA[0]
EMIF_BA[1]/N2HET2[5]
EMIF_ADDR[0]/N2HET2[1]
EMIF_ADDR[1]/N2HET2[3]
ETMDATA[11]/EMIF_ADDR[2]
ETMDATA[10]/EMIF_ADDR[3]
ETMDATA[9]/EMIF_ADDR[4]
ETMDATA[8]/EMIF_ADDR[5]
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]
EMIF_ADDR[9]/RTP_DATA[10]
EMIF_ADDR[10]/RTP_DATA[9]
EMIF_ADDR[11]/RTP_DATA[8]
EMIF_ADDR[12]/RTP_DATA[6]
EMIF_ADDR[13]/RTP_DATA[5]
EMIF_ADDR[14]/RTP_DATA[4]
EMIF_ADDR[15]/RTP_DATA[3]
EMIF_ADDR[16]/RTP_DATA[2]
EMIF_ADDR[17]/RTP_DATA[1]
EMIF_ADDR[18]/RTP_DATA[0]
EMIF_ADDR[19]/RTP_nENA
EMIF_ADDR[20]/RTP_nSYNC
EMIF_ADDR[21]/RTP_CLK
E12
Pulldown
P3
I/O
Pullup
D17 Output
R4 Output
Pullup
R3 Output
N17 Output Pulldown
L17 Output
Pullup
K17 Output Pulldown
M17 Output
Pullup
E10 Output
E11 Output
None
Fixed 20-µA
Pullup
E13 Output
D16 Output
D4 Output
D5 Output
E6 Output
E7 Output
E8
Output _Pulldown
E9 Output
C4 Output
C5 Output
C6 Output
C7 Output
C8 Output
C9 Output
C10 Output
C11 Output
C12 Output
C13 Output
D14 Output
C14 Output
D15 Output
C15 Output Pulldown
C16 Output
C17 Output
None
DESCRIPTION
EMIF Clock Enable
EMIF clock. This is an output
signal in functional mode. It is
gated off by default, so that
the signal is tri-stated.
PINMUX29[8] must be
cleared to enable this output.
EMIF Output Enable
EMIF Extended Wait Signal
EMIF Write Enable.
EMIF column address strobe
EMIF row address strobe
EMIF chip select, SDRAM
EMIF chip selects,
asynchronous
This applies to chip selects 2,
3, and 4
EMIF Data Mask or Write
Strobe.
Data mask for SDRAM
devices, write strobe for
connected asynchronous
devices.
EMIF bank address or
address line
EMIF bank address or
address line
EMIF address
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Terminal Configuration and Functions
31