PCM1748_15 Datasheet, PDF (31/38 Pages) Texas Instruments – Audio Digital-to-Analog Converter

www.ti.com
DATE REV
Apr 2005 B
PCM1748
PAGE
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2
2
2
4
6
9
12
12
13, 14
17
17, 18
20
24
25
26, 27
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REVISION HISTORY
SBAS165B – MAY 2001 – REVISED APRIL 2005
SECTION
Global
Absolute Maximum Ratings
Package/Ordering Information
Recommended Operating Con-
ditions
Electrical Characteristics
Pin Assignments and Terminal
Functions
Typical Performance Curves
Power-On-Reset Functions
Audio Serial Interface
Audio Data Formats and Timing
Register Map
Register Definitions
Register Definitions
Zero Flags
Connection Diagram
PCB Layout Guidelines
Dynamic Range
DESCRIPTION
Changed to new format
Changed values for power supply voltage, digital input voltage, lead
temperature, and package temperature. Added supply voltage
difference, V_CC – V_DD < 3 V.
Table removed from page 2, reformatted, and appended at end of
data sheet.
New table added to data sheet.
Storage temperature removed from Temperature Range section of
Electrical Characteristics (duplicate information in Absolute Maxi-
mum Ratings).
Moved from page 2
In Figure 12, changed Y-axis label from SNR to Dynamic Range.
Added description about 1024-system-clock delay time shown in the
Figure 20 timing diagram.
Changed description of I²S format and condition for synchronization
from one SCK clock to three BCK clocks.
In Figure 21, Audio Data Input Formats, removed 32-f_S availability
from left-justified format. In Figure 22, Audio Interface Timing,
corrected specification for BCK pulse cycle time.
For Table 3, Mode Control Register Map, added note to explain the
RSV table entry.
For ATx[7:0] – Digital Attenuation Level Setting and MUTx – Soft
Mute Control, added description about incrementing/decrementing
attenuation level by one step for every 8/f_S period.
For FMT[2:0] – Audio Interface Data Format, corrected default
setting from 000, 24-bit standard format, right-justified data to 101,
left-justified format, 16-to 24-bit.
Added description for L-channel/R-channel common zero flag.
In Figure 28, corrected capacitor polarity for V_DD decoupling
capacitor.
In Figure 30 and Figure 31, deleted extraneous signal lines. In
Figure 31, changed leftmost block to Digital Logic and Audio
Processor.
Corrected parameters in test setup diagram, Figure 36.
31