OPA2830 Datasheet, PDF (31/43 Pages) National Semiconductor (TI) – Dual, Low-Power, Single-Supply, Wideband OPERATIONAL AMPLIFIER

OPA2830
www.ti.com.................................................................................................................................................. SBOS309D – AUGUST 2004 – REVISED AUGUST 2008
Dividing this expression by the noise gain
(NG = (1 + R_F/R_G)) will give the equivalent
input-referred spot noise voltage at the noninverting
input, as shown in Equation 2:
Ǹ ǒ Ǔ E_N +
2
E_NI2
)
ǒ_IBNR
Ǔ²
S
)
4kTR_S
)
I_BIR_F
NG
)
4kTR_F
NG
(2)
Evaluating these two equations for the circuit and
component values shown in Figure 70 will give a total
output spot noise voltage of 19.3nV/√Hz and a total
equivalent input spot noise voltage of 9.65nV/√Hz.
This is including the noise added by the resistors.
This total input-referred spot noise voltage is not
much higher than the 9.2nV/√Hz specification for the
op amp voltage noise alone.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output DC
accuracy in a wide variety of applications. The
power-supply current trim for the OPA2830 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output DC error
caused by this current. This is done by matching the
DC source resistances appearing at the two inputs.
Evaluating the configuration of Figure 72 (which has
matched DC input resistances), using worst-case
+25°C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to:
• (NG = noninverting signal gain at DC)
• ±(NG × V_OS(MAX)) + (R_F × I_OS(MAX))
• = ±(2 × 7.5mV) נ(375Ω × 1.1µA)
• = ±15.41mV
A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques
are available for introducing DC offset control into an
op amp circuit. Most of these techniques are based
on adding a DC current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
be noninverting, the offset control is best applied as
an inverting summing signal to avoid interaction with
the signal source. If the signal path is intended to be
inverting, applying the offset control to the
noninverting input may be considered. Bring the DC
offsetting current into the inverting input node through
resistor values that are much larger than the signal
path resistors. This will insure that the adjustment
circuit has minimal effect on the loop gain and hence
the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (T_J) is given by
T_A + P_D × θ_JA. The total internal power dissipation
(P_D) is the sum of quiescent power (P_DQ) and
additional power dissipated in the output stage (P_DL)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total supply
voltage across the part. P_DL will depend on the
required output signal and load; though, for resistive
loads connected to mid-supply (V_S/2), P_DL is at a
maximum when the output is fixed at a voltage equal
to V_S/4 or 3V_S/4. Under this condition, P_DL = V_S2/(16
× R_L), where R_L includes feedback network loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum T_J
using an OPA2830 (MSOP-8 package) in the circuit
of Figure 72 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω
load at +2.5V_DC on both outputs.
ƪ ƫ P_D + 10V
11.9mA ) 2 _ǒ16
5²
ǒ_{150W ø 1500W}ǓǓ
+ 142mW
Maximum T_J + ) 85^oC ) ^ǒ0.142W 150^oCńW^Ǔ + 106^oC
Although this is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
dissipation will occur if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
puts a high current through a large internal voltage
drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a
high-frequency amplifier like the OPA2830 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional
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