AFE5809_14 Datasheet, PDF (31/100 Pages) Texas Instruments – Fully Integrated, 8-Channel Ultrasound Analog Front End With Passive CW Mixer, andD igital I/Q Demodulator

AFE5809
www.ti.com
SLOS738D – SEPTEMBER 2012 – REVISED JANUARY 2014
ADDRESS
(DEC)
3[9:11]
3[12]
3[14:13]
3[15]
4[1]
4[3]
4[4]
5[13:0]
10[8]
13[9:0]
13[15:11]
15[9:0]
15[15:11]
17[9:0]
17[15:11]
19[9:0]
19[15:11]
21[0]
21[4:1]
22[0]
25[9:0]
25[15:11]
27[9:0]
27[15:11]
29[9:0]
29[15:11]
31[9:0]
31[15:11]
Table 5. ADC Register Map (continued)
ADDRESS
(HEX)
0x3[9:11]
0x3[12]
0x3[14:13]
0x3[15]
0x4[1]
0x4[3]
0x4[4]
0x5[13:0]
0xA[8]
0xD[9:0]
0xD[15:11]
0xF[9:0]
0xF[15:11]
0x11[9:0]
0x11[15:11]
0x13[9:0]
0x13[15:11]
0x15[0]
0x15[4:1]
0x16[0]
0x19[9:0]
0x19[15:11]
0x1B[9:0]
0x1B[15:11]
0x1D[9:0]
0x1D[15:11]
0x1F[9:0]
0x1F[15:11]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FUNCTION
RESERVED
DIGITAL_GAIN_ENABLE
SERIALIZED_DATA_RATE
ENABLE_EXTERNAL_
REFERENCE_MODE
ADC_RESOLUTION_SELECT
ADC_OUTPUT_FORMAT
LSB_MSB_FIRST
CUSTOM_PATTERN
SYNC_PATTERN
OFFSET_CH1
DIGITAL_GAIN_CH1
OFFSET_CH2
DIGITAL_GAIN_CH2
OFFSET_CH3
DIGITAL_GAIN_CH3
OFFSET_CH4
DIGITAL_GAIN_CH4
DIGITAL_HPF_FILTER_ENABLE
_ CH1-4
DIGITAL_HPF_FILTER_K_CH1-4
EN_DEMOD
OFFSET_CH8
DIGITAL_GAIN_CH8
OFFSET_CH7
DIGITAL_GAIN_CH7
OFFSET_CH6
DIGITAL_GAIN_CH6
OFFSET_CH5
DIGITAL_GAIN_CH5
DESCRIPTION
Set to 0
0: No digital gain;
1: Digital gain Enabled
Serialization factor
00: 14x
01: 16x
10: reserved
11: 12x
when 4[1] = 1. In the 16x serialization rate, two 0s are filled at two LSBs (see
Table 4). Note: Make sure the settings aligning with the demod register
0x3[14:13]. Please also aware that the same setting , for example "00", in
these two registers can represent different LVDS data rates respectively.
0: Internal reference mode;
1: Set to external reference mode
Note: Both 3[15] and 1[13] should be set as 1 when configuring the device in
the external reference mode
0: 14 bit;
1: 12 bit
0: 2's complement;
1: Offset binary
Note: When the demodulation feature is enabled, only 2's complement
format can be selected.
0: LSB first;
1: MSB first
Custom pattern data for LVDS output (2[15:13] = 011)
0: Test pattern outputs of 8 channels are NOT synchronized.
1: Test pattern outputs of 8 channels are synchronized.
Value to be subtracted from channel 1 code
0 to 6 dB in 0.2-dB steps
value to be subtracted from channel 2 code
0 to 6 dB in 0.2-dB steps
value to be subtracted from channel 3 code
0 to 6 dB in 0.2-dB steps
value to be subtracted from channel 4 code
0 to 6 dB in 0.2-dB steps
0: Disable the digital HPF filter;
1: Enable for 1-4 channels
Note: This HPF feature is only available when the demodulation block is
disabled.
Set K for the high-pass filter (k from 2 to 10, that is 0010B to 1010B).
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2^k/(2^k + 1) [x(n) – x(n – 1) + y(n – 1)] (please see Table 6)
0: Digital demodulator is enabled
1: Digital demodulator is disabled
Note: The demodulator registers can be reset when 0x16[0] is set as '0'. Thus
it is required to reconfigure the demodulator registers after toggling the
0x16[0].
value to be subtracted from channel 8 code
0 to 6-dB in 0.2-dB steps
value to be subtracted from channel 7 code
0 to 6-dB in 0.2-dB steps
value to be subtracted from channel 6 code
0 to 6-dB in 0.2-dB steps
value to be subtracted from channel 5 code
0 to 6-dB in 0.2-dB steps
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