LM3S9D96_16 Datasheet, PDF (304/1412 Pages) Texas Instruments – Stellaris LM3S9D96 Microcontroller

Internal Memory
6.2.3.1
6.2.3.2
Caution – The Stellaris Flash memory array has ECC which uses a test port into the Flash memory to
continually scan the array for ECC errors and to correct any that are detected. This operation is
transparent to the microcontroller. The BIST must scan the entire memory array occasionally to ensure
integrity, taking about five minutes to do so. In systems where the microcontroller is frequently powered
for less than five minutes, power should be removed from the microcontroller in a controlled manner
to ensure proper operation. Software can request permission to power down the part using the USDREQ
bit in the Flash Control (FCTL) register and wait to receive an acknowledge from the USDACK bit prior
to removing power. If the microcontroller is powered down using this controlled method, the BIST
engine keeps track of where it was in the memory array and it always scans the complete array after
any aggregate of five minutes powered-on, regardless of the number of intervening power cycles. If the
microcontroller is powered down before five minutes of being powered up, BIST starts again from
wherever it left off before the last controlled power-down or from 0 if there never was a controlled
power down. An occasional short power down is not a concern, but the microcontroller should not
always be powered down frequently in an uncontrolled manner. The microcontroller can be power-cycled
as frequently as necessary if it is powered-down in a controlled manner.
Prefetch Buffer
The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency
is greater than 50 MHz. In this mode, the Flash memory operates at half of the system clock. The
prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait
states while code is executing linearly. The fetch buffer includes a branch speculation mechanism
that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short
loop branches often stay in the buffer. As a result, some branches can be executed with no wait
states. Other branches incur a single wait state.
Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in eight
pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 6-1 on page 304.
Table 6-1. Flash Memory Protection Policy Combinations
FMPPEn
0
1
0
1
FMPREn
0
0
1
1
Protection
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
No protection. The block may be written, erased, executed or read.
304
July 03, 2014
Texas Instruments-Production Data