TLV320AIC3256_14 Datasheet, PDF (30/45 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec With Embedded miniDSP

TLV320AIC3256
SLOS630A – DECEMBER 2010 – REVISED DECEMBER 2010
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The TLV320AIC3256 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0,
Register 28.
The TLV320AIC3256 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen. This can be configured via Page 0, Register 29, D(3).
The TLV320AIC3256 further includes programmability (Page 0, Register 27, D0) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3256, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word-clock or bit-clocks are used in the system as general-purpose clocks.
Clock Generation and PLL
The TLV320AIC3256 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the
miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference
clocks on MCLK BCLK or GPIO, the TLV320AIC3256 also provides the option of using the on-chip PLL which
supports a wide range of fractional multiplication values to generate the required clocks. Starting from
CODEC_CLKIN the TLV320AIC3256 provides several programmable clock dividers to help achieve a variety of
sampling rates for ADC, DAC and clocks for the miniDSP .
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3256.
For more detailed information see the Application Reference Guide, SLAU306
Control Interfaces
The TLV320AIC3256 control interface supports SPI or I²C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I²C, SPI_SELECT should be tied low.
It is not recommended to change the state of SPI_SELECT during device operation.
I²C Control
The TLV320AIC3256 supports the I²C control protocol, and will respond to the I²C address of 0011000. I²C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
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