ADS8861IDGS Datasheet, PDF (30/48 Pages) Texas Instruments – 16-Bit 1-MSPS Serial Interface microPower Miniature True-Differential Input SAR Analog-to-Digital Converter

ADS8861
SBAS557A – MAY 2013 – REVISED DECEMBER 2013
APPLICATION INFORMATION
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The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, followed by some application circuits
designed using the ADS8861.
ADC REFERENCE DRIVER
The external reference source to the ADS8861 must provide low-drift and very accurate voltage for the ADC
reference input and support the dynamic charge requirements without affecting the noise and linearity
performance of the device. The output broadband noise of most references can be in the order of a few 100
μV_RMS. Therefore, to prevent any degradation in the noise performance of the ADC, the output of the voltage
reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few hundred Hertz.
After band-limiting the noise of the reference circuit, the next important step is to design a reference buffer that
can drive the dynamic load posed by the reference input of the ADC. The reference buffer must regulate the
voltage at the reference pin such that the value of V_REF stays within the 1-LSB error at the start of each
conversion. This condition necessitates the use of a large capacitor, C_{BUF_FLT} (refer to Figure 48) for regulating
the voltage at the reference input of the ADC. The amplifier selected to drive the reference pin should have an
extremely low offset and temperature drift with a low output impedance to drive the capacitor at the ADC
reference pin without any stability issues.
Reference Driver Circuit for V_REF = 4.5 V
The application circuit in Figure 67 shows the schematic of a complete reference driver circuit that generates a
voltage of 4.5 V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8861 at
higher sampling rates up to 1 MSPS. The 4.5-V reference voltage in this design is generated by the high-
precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-
pass filter with a 3-dB cutoff frequency of 160 Hz.
20 k
1 µF
AVDD
REF5045
Vin Vout
Temp
Gnd Trim
1 µF
1 k
1 µF
-
1 k
+ ⁺ _OPA333
AVDD
1 µF
-
+ ⁺ _THS4281
AVDD
0.2
10 µF
AVDD
REF AVDD
AVINP
CONVST
+
ADS8861
AINM
GND
Figure 67. Schematic of Reference Driver Circuit with V_REF = 4.5 V
The reference buffer is designed with the THS4281 and OPA333 in a composite architecture to achieve superior
dc and ac performance at a reduced power consumption, compared to using a single high-performance amplifier.
The THS4281 is a high-bandwidth amplifier with a very low output impedance of 1 Ω at a frequency of 1 MHz.
The low output impedance makes the THS4281 a good choice for driving a high capacitive load to regulate the
voltage at the reference input of the ADC. The high offset and drift specifications of the THS4281 are corrected
by using a dc-correcting amplifier (OPA333) inside the feedback loop. The composite scheme inherits the
extremely low offset and temperature drift specifications of the OPA333.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, using a similar device, refer to 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step
Response (SLAU512).
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