ADS8331_14 Datasheet, PDF (30/47 Pages) Texas Instruments – Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface

ADS8331
ADS8332
SBAS363C – DECEMBER 2009 – REVISED MAY 2012
INT
CS1
MICROCONTROLLER
CS2
CS3
SDO SCLK
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SDI
SDI SCLK CONVST
CS _ADS8331/32
#1
EOC/INT
SDO
SDI SCLK CONVST
CS
ADS8331/32
#2
CDI
SDO
SDI SCLK CONVST
CS _ADS8331/32
#3
CDI
SDO
Program Device #1: CFR_D5 = ‘1’
Program Devices #2 and #3: CFR_D5 = ‘0’
Figure 46. Multiple Converters Connected Using Daisy-Chain Mode
When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while
the rest of the converters downstream are configured in daisy-chain mode. When a converter is configured in
daisy-chain mode, the CDI input data go straight to the output register. Therefore, the serial input data passes
through the converter with either a 16 SCLK (if the TAG feature is disabled) or 24 SCLK delay, as long as CS is
active. See Figure 47 for detailed timing. In this timing diagram, the conversion in each converter is performed
simultaneously.
Manual Trigger, Read While Sampling
(Use internal CCLK, EOC active low, and TAG mode disabled)
CONVST #1
CONVST #2
CONVST #3
EOC #1
(active low)
CS #1
SCLK #1
SCLK #2
SCLK #3
SDO #1
CDI #2
CS #2
CS #3
Conversion N
t_CONV = 18 CCLK
High-Z
1. . . . . . . . . . . . . .16
Conversion N
from Device #1
t_SAMPLE1 = 3 CCLK min
1. . . . . . . . . . . . . .16
1. . . . . . . . . . . . . .16
t_SU2
High-Z
t_SU2
SDO #2
CDI #3
High-Z
Conversion N
from Device #2
Conversion N
from Device #1
High-Z
SDO #3
High-Z
Conversion N
from Device #3
Conversion N
from Device #2
Conversion N
from Device #1
High-Z
SDI #1
SDI #2
SDI #3
Don't Care
Configure
Read Data
Read Data
Don't Care
Figure 47. Simplified Dasiy-Chain Mode Timing with Shared CONVST and Continuous CS
The multiple CS signals must be handled with care when the converters are operating in daisy-chain mode. The
different chip select signals must be low for the entire data transfer (in this example, 48 bits for three
conversions). The first 16-bit word after the falling chip select is always the data from the chip that received the
chip select signal.
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